From patchwork Fri May 3 12:37:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 163323 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp554054ill; Fri, 3 May 2019 05:38:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqyceiDP9lR2rgfEVo7aFpse7FlEB/R8BktXniA76H8lOLKtSn6i9DTcXWTrEAP6SMX1gpos X-Received: by 2002:a17:902:2a07:: with SMTP id i7mr4230559plb.125.1556887102904; Fri, 03 May 2019 05:38:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556887102; cv=none; d=google.com; s=arc-20160816; b=AH4hpfp7WHcUUkGOMsXX+uKIm8Y6RlesT5zHwzfnj8FN5QBTqkHwefsax87PEpOiTn sk9L7SJ1ckhuZ41HGg10qB3SuMFykiL2O1ModJq61+PohyfcMWG/pcoC0ZcvWb9eg/fA +Ze+jhX0Du+mVcvy57TmQN56Wzd1gYGpGrXDuVsFjwllh9FArvVl75y4DyNvYxjIhzp3 IVEEv9ci2IpT4QN72q4dLXxzGUiy+zFZQSru+k++as9pxmqz4k70yNuoDPXS6OwUfoYC 50okW9rtmxVZVQqeI+Or846qvP83CBNz2/oM5duXZJbCRdNj41o/0AEdZA9zbSDEv7X7 5j0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=N7oCkXQfepu6l+UAHVtt5vfxPNB5K7tbRYmyelOMNYM=; b=dIZGw6WMx9ItVESQQRPaIuiOgaf8xjRMDmKa4YiIOH0iOCqZc7H1BhdUqhPzrWfZrX ynGTxDzH5yd19zsecUVwbiffAG5/7rkMM9rwjmODvuR1P47lOPWz4C4wrhfrZKJ+bnzk CjSnVz14YrBTSYw4crSRBrCCeNvElOa6eqfGk8GByUEUqQQ0Chh2Zy6I2sgsepD26W/H Tn4mdkB2MAnzUzpJskwWcNfbQCTSQONydLeKbVRcXEvGJcntIdrltDbJqWPU61MqEG5H PldDDxQX/OrIPffPxIv1h8ZPIFgCeUf+EEzcsdOciYYdtTcDa6kg8vSoLBQjbRPEYSDn 0+0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=utdjWpxm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q3si2279871plb.266.2019.05.03.05.38.22; Fri, 03 May 2019 05:38:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=utdjWpxm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727874AbfECMiV (ORCPT + 30 others); Fri, 3 May 2019 08:38:21 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:35957 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726897AbfECMiV (ORCPT ); Fri, 3 May 2019 08:38:21 -0400 Received: from grover.flets-west.jp (softbank126125154139.bbtec.net [126.125.154.139]) (authenticated) by conuserg-07.nifty.com with ESMTP id x43CbuW9020722; Fri, 3 May 2019 21:37:57 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x43CbuW9020722 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1556887077; bh=N7oCkXQfepu6l+UAHVtt5vfxPNB5K7tbRYmyelOMNYM=; h=From:To:Cc:Subject:Date:From; b=utdjWpxmGnVSZlPDbdmUSctuhbvdk/+xastR2qAA9SFYQC9pF8dDKTe07nQv3bnSK n1IsL8kt+BBPcpKV/aAJcexyRpu0CLMhflaktEF8LVR2EvMfCV5VwBPILgeeNlOpPB FoAtf3f1tLGfqy1tjdIohPQfR6JbVfEENM6gAUrmEBCwvP0dbte8eJGU+BfTIcCuzz 397zHtom+oyAWBXgbje71WSOWgaEm9YDrt/wQU9eShTtElu32YlQ1BvkXDd+98ik0f gnBEede0sb/LLcyjg6eMdWYMh0IgHCv+GYNZjq/vS0LKZBRUG1mXHPeJ9bSxKA7mV6 b6qQX/b1d8ERA== X-Nifty-SrcIP: [126.125.154.139] From: Masahiro Yamada To: Andrew Morton Cc: x86@kernel.org, linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, Masahiro Yamada Subject: [PATCH] x86, sh: use __builtin_constant_p() directly instead of IS_IMMEDIATE() Date: Fri, 3 May 2019 21:37:44 +0900 Message-Id: <1556887064-12882-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org __builtin_constant_p(nr) is used everywhere now. It does not make much sense to define IS_IMMEDIATE() as its alias. Signed-off-by: Masahiro Yamada --- arch/sh/include/asm/bitops-op32.h | 8 +++----- arch/x86/include/asm/bitops.h | 7 +++---- 2 files changed, 6 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/arch/sh/include/asm/bitops-op32.h b/arch/sh/include/asm/bitops-op32.h index 4668803..cfe5465 100644 --- a/arch/sh/include/asm/bitops-op32.h +++ b/arch/sh/include/asm/bitops-op32.h @@ -16,11 +16,9 @@ #define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE) #endif -#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr)) - static inline void __set_bit(int nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bset.b %1, @(%O2,%0) ! __set_bit\n\t" : "+r" (addr) @@ -37,7 +35,7 @@ static inline void __set_bit(int nr, volatile unsigned long *addr) static inline void __clear_bit(int nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bclr.b %1, @(%O2,%0) ! __clear_bit\n\t" : "+r" (addr) @@ -64,7 +62,7 @@ static inline void __clear_bit(int nr, volatile unsigned long *addr) */ static inline void __change_bit(int nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bxor.b %1, @(%O2,%0) ! __change_bit\n\t" : "+r" (addr) diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 8e790ec..2621438 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -45,7 +45,6 @@ * We do the locked ops that don't return the old value as * a mask operation on a byte. */ -#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr)) #define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3)) #define CONST_MASK(nr) (1 << ((nr) & 7)) @@ -67,7 +66,7 @@ static __always_inline void set_bit(long nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "orb %1,%0" : CONST_MASK_ADDR(nr, addr) : "iq" ((u8)CONST_MASK(nr)) @@ -105,7 +104,7 @@ static __always_inline void __set_bit(long nr, volatile unsigned long *addr) static __always_inline void clear_bit(long nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "andb %1,%0" : CONST_MASK_ADDR(nr, addr) : "iq" ((u8)~CONST_MASK(nr))); @@ -186,7 +185,7 @@ static __always_inline void __change_bit(long nr, volatile unsigned long *addr) */ static __always_inline void change_bit(long nr, volatile unsigned long *addr) { - if (IS_IMMEDIATE(nr)) { + if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "xorb %1,%0" : CONST_MASK_ADDR(nr, addr) : "iq" ((u8)CONST_MASK(nr)));