From patchwork Mon Dec 17 17:21:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 154028 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2716400ljp; Mon, 17 Dec 2018 09:22:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/UOIUYsYMTEpaV+uUUkdbixtNDY0SkFHTG0nSySUZTKPdM7hqIjN9SJZglhy0Fd+o6GH0M/ X-Received: by 2002:a62:cf02:: with SMTP id b2mr14109669pfg.183.1545067340054; Mon, 17 Dec 2018 09:22:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545067340; cv=none; d=google.com; s=arc-20160816; b=uCZctZuPFItJdQphOsxULBK9FYjJQTBC2VAt4/2olBsAEcvNN+ev9lhpWNH6p3vUGg U+xehrPuDgJ9saD6hqzcn1EEUtZV0LiUKxFnnYpNjuK84HDPfqgzLS8HWwgwnL4NmfJA TRdawTdYSMsyFVTdF63GFAr9FohkRBUisfLN8DWrAySH6ESPn9YzjHETKfVkATXQ8tNt TIE0KLW9M7EM8e/Ai03H+zvaxiQ90diPPeeVK7BIlNUKF0CNv+w3wlvo3vMF81/U/17E 5FuGsFtr296wo4MySXox5mz2nefkKaMeit2MbYww7IMQAGHJbRBPgn8Njiz/QKLuu/Bp 3Qjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=vffhfUlrlCExin749UjB4Nm/CBeftT0GbW0095v/Xho=; b=w4aYYTLDZakkvUNvXdXEvUa2weD95Ha9PADwCCq/6XbkpgGuwuL+brFgGkaCFpqkns xY6R4D4LjBuYnhJ64UVpGAyGKjM+Z5YCU8YOmiTukZM4BvTH0oFl3n2fDFEecktISZCN WsQodyAJTHWq2MWKMo8IoMGZk7l9y4YDI4BC1sdrdopHyPbTxncy95xrxLUzCHdkqm01 7YpPaVQWR8YquQ6hhXxkwl31ttv02X5swPq1eYlcDEl9Mx4A5MjmUNosrWPZgwgG/VJI N6NdSPme/jjZ4UjIIazXjd4Y2TDRzuKw/L1QWuZpBRe/5gbom/e4e2jYykKeznsmJFhj Y1bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C+6xK+0a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r17si11117837pls.380.2018.12.17.09.22.19; Mon, 17 Dec 2018 09:22:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C+6xK+0a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388410AbeLQRWR (ORCPT + 31 others); Mon, 17 Dec 2018 12:22:17 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:43950 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388354AbeLQRV5 (ORCPT ); Mon, 17 Dec 2018 12:21:57 -0500 Received: by mail-pl1-f196.google.com with SMTP id gn14so6435618plb.10 for ; Mon, 17 Dec 2018 09:21:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vffhfUlrlCExin749UjB4Nm/CBeftT0GbW0095v/Xho=; b=C+6xK+0a+lPk9/Jka+QJIqeB/MDgk+NIwssQyhCsdKazJTK6n7oJHufE+4M2VUaOta VuCjWVMB0oSrl6eYfOVL2IMEbPjH9hRfS3UyN2MKJx6Bz1TAu1BJaQ8+hJsCkFxVmDEG n4zktOwuQ/RU4YR/amHmjcaCwvJTzliiG4kyI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vffhfUlrlCExin749UjB4Nm/CBeftT0GbW0095v/Xho=; b=ZDmWZeTLOvYyurwE3gfv3Jyqcj2P0tkCUkPmkC88w1XNIZTwmMFc7OpX9XA8Z+avz6 N5jHFKgHkD+QBi13Q/T7XQK8YWzjV6qBeTddWOGhp5G+k9E684LJO8jfvZ7+HpL50yKX MhyKgDNo9zguGqSzzi1jAVuWkAELRlQHXrT8uBkXWPhdUwfHIhK05YPygcd9h0FE6FE0 8I1tm/3xCdNcwlJ7bzMhME5zmIBaEXThWlyeaXmNUDKjONfdcJLpdupbYetpS1MDpo1I TSj2zOcjaicRJOvrzrH0z4qPOe8+dXKlgLVpBF/MmhD6pw5qkxumaKROlnrYRUpR+LJL PxQw== X-Gm-Message-State: AA+aEWbKxPntRZyYmmtaT7oTC7q7vqEz/m3+pe9puGpqB0ieOe5f/Mlc FQlcY0QucqRPf4j8LVCA5FbE+g== X-Received: by 2002:a17:902:9a9:: with SMTP id 38mr13171952pln.204.1545067316335; Mon, 17 Dec 2018 09:21:56 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id j6sm20526648pfg.126.2018.12.17.09.21.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 09:21:55 -0800 (PST) From: Mathieu Poirier To: acme@kernel.org, peterz@infradead.org, gregkh@linuxfoundation.org Cc: mingo@redhat.com, tglx@linutronix.de, alexander.shishkin@linux.intel.com, schwidefsky@de.ibm.com, heiko.carstens@de.ibm.com, will.deacon@arm.com, mark.rutland@arm.com, jolsa@redhat.com, namhyung@kernel.org, adrian.hunter@intel.com, ast@kernel.org, hpa@zytor.com, suzuki.poulosi@arm.com, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH v5 4/6] coresight: Use PMU driver configuration for sink selection Date: Mon, 17 Dec 2018 10:21:44 -0700 Message-Id: <1545067306-31687-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545067306-31687-1-git-send-email-mathieu.poirier@linaro.org> References: <1545067306-31687-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch uses the PMU driver configuration held in event::hw::drv_config to select a sink for each event that is created (the old sysFS way of working is kept around for backward compatibility). By proceeding in this way a sink can be used by multiple sessions without having to play games with entries in sysFS. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 74 ++++++++++++++++++++---- 1 file changed, 62 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index f21eb28b6782..a7e1fdef07f2 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -11,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -177,6 +179,26 @@ static void etm_free_aux(void *data) schedule_work(&event_data->work); } +static struct coresight_device *etm_drv_config_sync(struct perf_event *event) +{ + struct coresight_device *sink = NULL; + struct pmu_drv_config *drv_config = perf_event_get_drv_config(event); + + /* + * Make sure we don't race with perf_drv_config_replace() in + * kernel/events/core.c. + */ + raw_spin_lock(&drv_config->lock); + + /* Copy what we got from user space if applicable. */ + if (drv_config->config) + sink = drv_config->config; + + raw_spin_unlock(&drv_config->lock); + + return sink; +} + static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { @@ -190,18 +212,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, return NULL; INIT_WORK(&event_data->work, free_event_data); - /* - * In theory nothing prevent tracers in a trace session from being - * associated with different sinks, nor having a sink per tracer. But - * until we have HW with this kind of topology we need to assume tracers - * in a trace session are using the same sink. Therefore go through - * the coresight bus and pick the first enabled sink. - * - * When operated from sysFS users are responsible to enable the sink - * while from perf, the perf tools will do it based on the choice made - * on the cmd line. As such the "enable_sink" flag in sysFS is reset. - */ - sink = coresight_get_enabled_sink(true); + /* First get the sink config from user space. */ + sink = etm_drv_config_sync(event); + if (!sink) + sink = coresight_get_enabled_sink(true); + if (!sink || !sink_ops(sink)->alloc_buffer) goto err; @@ -454,6 +469,40 @@ static void etm_addr_filters_sync(struct perf_event *event) filters->nr_filters = i; } +static int etm_drv_config_find_sink(struct device *dev, void *data) +{ + struct amba_device *adev = to_amba_device(dev->parent); + struct resource *res = &adev->res; + u64 value = *((u64 *)data); + + /* + * The HW mapping of a component is unique. If the value we've been + * given matches the component's start address, then we must have found + * the device we are looking for. + */ + if (res->start == value) + return 1; + + return 0; +} + +static void *etm_drv_config_validate(struct perf_event *event, u64 value) +{ + struct device *dev; + struct coresight_device *sink; + + /* Look for the device with a res->start equal to @value. */ + dev = bus_find_device(&coresight_bustype, NULL, + &value, etm_drv_config_find_sink); + if (!dev) + return ERR_PTR(-EINVAL); + + sink = to_coresight_device(dev); + put_device(dev); + + return sink; +} + int etm_perf_symlink(struct coresight_device *csdev, bool link) { char entry[sizeof("cpu9999999")]; @@ -498,6 +547,7 @@ static int __init etm_perf_init(void) etm_pmu.addr_filters_sync = etm_addr_filters_sync; etm_pmu.addr_filters_validate = etm_addr_filters_validate; etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; + etm_pmu.drv_config_validate = etm_drv_config_validate; ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); if (ret == 0)