From patchwork Fri Nov 9 14:06:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 150652 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp212971ljp; Fri, 9 Nov 2018 06:07:33 -0800 (PST) X-Google-Smtp-Source: AJdET5eP4+XF9A+hATpKeOGmGWoNC1Nd4baxhYboZGSaiX47Nu22HDvPED/Xz35oNi3w5FR+X9U+ X-Received: by 2002:a17:902:2006:: with SMTP id n6-v6mr9181640pla.131.1541772452966; Fri, 09 Nov 2018 06:07:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541772452; cv=none; d=google.com; s=arc-20160816; b=UxudlmQrEBGdof30cjUawyqOT2BzLMJgr/9zNo1LDECvTlQTeBxOAJzDDY7CpCt3eL HW0GmnTvln9w2HEtRHgK+8uT4jX/hQvyNeZZrM6RDC0nVs9U1StD8o56u4XkT40rt/4Z wDGSin6/XyvF1w8DS2eTjCTuDNNd2chaF/YFsC3NonGzA63AdUBCWptr8+q3s39H8yvV YERmIiE9P63NGPF0vwvSyYv7sWB3YzIL4eH6xibyydcqQi7KGhYdYVfN/nN/K7VAqYj7 wbxT3E5E95PPV1iolfAczQNMEctQqRCrVNjopYmHgscWbWL6nTwF3VExSjkCspqF3LvL dvxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=Du7KnrGyUsGPBLUIq506jdmzzIZU70I3xHUkRV2z4Ao=; b=Biq9o1CxjuEIfwT/EKkedZ9Bp9M+Yy7F9lLJr89yO1cLENjDojZt0rZFXjC5ZuCjIe rB4orc1CFFeTbqu3uML9RcTrCA4RDwaG61RIXUoB9pdK9OCc3L17yYMN3GY5V5f7FrFp Mlc/T5U92H9z9UZovASCJov3wUpbDGW67Vlf9LI6m6HYFYb3y/F7anDzqhxcKz9R27MK j8Q+ndawN/kZOmvUShPe6DBlHuyEl8pbokhh0B6U0IcUn9O4Npw2HcqeKHPdDe9sopfd OwDZYznEQ+gAqrckD7Jrmz7gdMyq9StkwitarrSBRKjsgWifCNG4mNiUwFfahO5E3eY0 efYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l184si6806759pgd.523.2018.11.09.06.07.21; Fri, 09 Nov 2018 06:07:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728376AbeKIXqU (ORCPT + 32 others); Fri, 9 Nov 2018 18:46:20 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:47755 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728237AbeKIXqU (ORCPT ); Fri, 9 Nov 2018 18:46:20 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id EF6015679302F; Fri, 9 Nov 2018 22:05:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.408.0; Fri, 9 Nov 2018 22:04:55 +0800 From: John Garry To: , CC: , , , Xiang Chen , John Garry Subject: [PATCH 3/5] scsi: hisi_sas: Add support for interrupt coalescing for v3 hw Date: Fri, 9 Nov 2018 22:06:34 +0800 Message-ID: <1541772396-161814-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1541772396-161814-1-git-send-email-john.garry@huawei.com> References: <1541772396-161814-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen If INT_COAL_EN is enabled, config time and count of interrupt coalescing. Then if CQ collects count of CQ entries in time, it will report the interrupt. Or if CQ doesn't collect enough CQ entries in time, it Will report the interrupt at timeout. As all the registers are not supported to be changed dynamically, so need to config those register between disable and enable PHYs. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 + drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 100 +++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 94a9e13..535c613 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -322,6 +322,8 @@ struct hisi_hba { unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)]; struct work_struct rst_work; u32 phy_state; + u32 intr_coal_ticks; /* Time of interrupt coalesce in us */ + u32 intr_coal_count; /* Interrupt count to coalesce */ }; /* Generic HW DMA host memory structures */ diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 10d1651..0c3fa43 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -2107,9 +2107,109 @@ static ssize_t intr_conv_v3_hw_show(struct device *dev, } static DEVICE_ATTR_RO(intr_conv_v3_hw); +static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) +{ + /* config those registers between enable and disable PHYs */ + hisi_sas_stop_phys(hisi_hba); + + if (hisi_hba->intr_coal_ticks == 0 || + hisi_hba->intr_coal_count == 0) { + hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); + } else { + hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, + hisi_hba->intr_coal_ticks); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, + hisi_hba->intr_coal_count); + } + phys_init_v3_hw(hisi_hba); +} + +static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct hisi_hba *hisi_hba = shost_priv(shost); + + return scnprintf(buf, PAGE_SIZE, "%u\n", + hisi_hba->intr_coal_ticks); +} + +static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct hisi_hba *hisi_hba = shost_priv(shost); + u32 intr_coal_ticks; + int ret; + + ret = kstrtou32(buf, 10, &intr_coal_ticks); + if (ret) { + dev_err(dev, "Input data of interrupt coalesce unmatch\n"); + return -EINVAL; + } + + if (intr_coal_ticks >= BIT(24)) { + dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); + return -EINVAL; + } + + hisi_hba->intr_coal_ticks = intr_coal_ticks; + + config_intr_coal_v3_hw(hisi_hba); + + return count; +} +static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); + +static ssize_t intr_coal_count_v3_hw_show(struct device *dev, + struct device_attribute + *attr, char *buf) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct hisi_hba *hisi_hba = shost_priv(shost); + + return scnprintf(buf, PAGE_SIZE, "%u\n", + hisi_hba->intr_coal_count); +} + +static ssize_t intr_coal_count_v3_hw_store(struct device *dev, + struct device_attribute + *attr, const char *buf, size_t count) +{ + struct Scsi_Host *shost = class_to_shost(dev); + struct hisi_hba *hisi_hba = shost_priv(shost); + u32 intr_coal_count; + int ret; + + ret = kstrtou32(buf, 10, &intr_coal_count); + if (ret) { + dev_err(dev, "Input data of interrupt coalesce unmatch\n"); + return -EINVAL; + } + + if (intr_coal_count >= BIT(8)) { + dev_err(dev, "intr_coal_count must be less than 2^8!\n"); + return -EINVAL; + } + + hisi_hba->intr_coal_count = intr_coal_count; + + config_intr_coal_v3_hw(hisi_hba); + + return count; +} +static DEVICE_ATTR_RW(intr_coal_count_v3_hw); + struct device_attribute *host_attrs_v3_hw[] = { &dev_attr_phy_event_threshold, &dev_attr_intr_conv_v3_hw, + &dev_attr_intr_coal_ticks_v3_hw, + &dev_attr_intr_coal_count_v3_hw, NULL };