From patchwork Fri Oct 5 14:35:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 148192 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp528199lji; Fri, 5 Oct 2018 07:36:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV60cxtGUwUGUUSAlYAERZ0+EklAajio9fwVoBuP0IRbzVquW3nqWA9wuFf20SDfkSj0rQCiR X-Received: by 2002:a17:902:7043:: with SMTP id h3-v6mr12035002plt.103.1538750206466; Fri, 05 Oct 2018 07:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538750206; cv=none; d=google.com; s=arc-20160816; b=LLZeEOoOpVBECqp/Hl1MQXGdUvi8QdOfbYKgjdvx3k0Yem3+Obw3FZt8C2Z5TpcEYW IMl94z/2/y5TOO4zwV/AT+QSYkoA8tETxDq+dnwr3UTujLjJp1dVM+9vAbK4agGU+Svo LE771pM4yADkFDDx+EFwT7VuHzRDOIEwGKidqkyvRRBt0xg3S1WMLHn6gUaqOzX8CEgQ l9pvCILWSEuG3Aq617D9Wgud/kveyZAo1oOpoYQnC/NAf/eREVWIFYzjn33MHHHsY8X0 2pEDVjw1RAcAeoyvRfNosQxOrFJXbd5b1/xqPY51r/W85T3c/BB3LP0aD5izkJv8GjfN WtUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=VhnOKWzkRDC+3They8IdOyuR0e/vVZiouL/bg+aJfrs=; b=qOj609eB3E+T5wobpJcG34ViG1Umf09Xc/yzZLRsX4t3fY/YZpeQcv0EbTySiakOIm rziZRcTv5GPGqH2/HJERk9C1n0/dT/0Ji0aVlVpjnuIPuAGdiAZ9TQVbWloFP+GR/YS6 ecYcN8uMaOXU2Xfet6q6tfaj6VE+0TwEzKJ1NrqIe6Rs8OkURxurN3oJDhx+AyY2bzl7 /zx8YA58byk5v2z9bHYq6eYqAJkMCmd3Cjox6vRCJT7lJyGTtpiUys0NU2vGYk67UYlP hFhnnC85bebOA7cdXh7G8Uwy0G7ncY2FLuM75aYBRUdLsOM83n4QxJnqRaEz7tI5WduZ CxYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IJhJWd6D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o125-v6si6161067pgo.302.2018.10.05.07.36.46; Fri, 05 Oct 2018 07:36:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IJhJWd6D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729238AbeJEVfn (ORCPT + 32 others); Fri, 5 Oct 2018 17:35:43 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:35896 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729202AbeJEVfm (ORCPT ); Fri, 5 Oct 2018 17:35:42 -0400 Received: by mail-wm1-f67.google.com with SMTP id a8-v6so2155543wmf.1 for ; Fri, 05 Oct 2018 07:36:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VhnOKWzkRDC+3They8IdOyuR0e/vVZiouL/bg+aJfrs=; b=IJhJWd6DGVNVQtroYCFeX+Lkih9gdQDXW3oqwKdHYWrnLB7xS5fvZO4G/XluSgqL4F jCiYPcd4tikJe7EYb1CvfvOOQMebNK29/8V8zEm9mX9kcwvy7vFqYs/MULN9GaRaFFdU L2jRgKWg/9StPows4tqoPsPbupCI7EAhaLKW0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VhnOKWzkRDC+3They8IdOyuR0e/vVZiouL/bg+aJfrs=; b=Zatjy15P4QaplXB8ExYM75o9XZiaPGsw1nMdCHmH2bTg3KKv/NZ6o++GKcgBqlVd4M 0e4m3qYH5KDkVgL/xINgqBO3e/Dgsc6O8QaRFZs1KEuizLS5lmTA+hACRRCjUpSMO/C6 Ju3o16iHCWwzmHk4pi79aVATSq5jG3xAY8GsMwZRleexQv/qFXcN6U4y9bKs6Td9NrZr o009SHaFoTxjYpzWkF+H0XXO87nksja0F7q1xyv8iFOoJfz7YmeVHHzMdjaooYhheqZ0 8akskjMFmBoUiznk5kMb1rokRRZWr3LCTPBW5pUJvShNtBbmFXVAS4Dk6pwA/KRq7Ozf I9Qw== X-Gm-Message-State: ABuFfoiIx4vlXUWOUJv+t62B8oV2VagrqI+VKX8FykaB8mNEx58/AnUy 42tSawv1KBIO43bsoRC18Wbrbg== X-Received: by 2002:a1c:6c09:: with SMTP id h9-v6mr7693290wmc.95.1538750201297; Fri, 05 Oct 2018 07:36:41 -0700 (PDT) Received: from localhost.localdomain (151.240.136.77.rev.sfr.net. [77.136.240.151]) by smtp.gmail.com with ESMTPSA id t24-v6sm14080377wra.5.2018.10.05.07.36.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Oct 2018 07:36:40 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dinh Nguyen , Marek Vasut Subject: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control Date: Fri, 5 Oct 2018 16:35:42 +0200 Message-Id: <1538750143-4282-13-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538750143-4282-1-git-send-email-daniel.lezcano@linaro.org> References: <20181005143253.GE1881@mai> <1538750143-4282-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dinh Nguyen Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset). This patch is needed for systems where the bootloader has left the timer not used in reset. - Trivial conflict with commit a74bd1ad7a: "Convert to using %pOFn instead of device_node.name" Signed-off-by: Marek Vasut Signed-off-by: Dinh Nguyen Signed-off-by: Daniel Lezcano --- drivers/clocksource/dw_apb_timer_of.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index fabaa29..db410ac 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -22,6 +22,7 @@ #include #include #include +#include #include static void __init timer_get_base_and_rate(struct device_node *np, @@ -29,6 +30,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, { struct clk *timer_clk; struct clk *pclk; + struct reset_control *rstc; *base = of_iomap(np, 0); @@ -36,6 +38,16 @@ static void __init timer_get_base_and_rate(struct device_node *np, panic("Unable to map regs for %pOFn", np); /* + * Reset the timer if the reset control is available, wiping + * out the state the firmware may have left it + */ + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); + } + + /* * Not all implementations use a periphal clock, so don't panic * if it's not present */