From patchwork Thu Sep 20 19:17:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 147144 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2376453ljw; Thu, 20 Sep 2018 12:19:02 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZf9hSFo5s6GnP0EmFTCK1z61yS6qgO8Oyb9pgEqtACU4p/6+0yxdSyZzVQqZonKGAO8Vab X-Received: by 2002:a63:d34f:: with SMTP id u15-v6mr8701363pgi.325.1537471141966; Thu, 20 Sep 2018 12:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537471141; cv=none; d=google.com; s=arc-20160816; b=X8AVPDq6fPp6/9Ngsyc5nb799sjCb9Rn8YtetPeG2xV+FKH5SgBGzSEHQmD2AqNAup 0aGElx5EnNgdkKfT/tAkvu7+cbpR2eCs5bMKh8Q1HD1sFcC1J/sPwY8OHWIFAtYBx0l8 1hu2kUI1ke3nG6AbwRUrossxwUdG6zHKJhkMgu+pysuo9a8e8Lf7XCUMClRO9s6kZts+ N3Z4Bk7EFAdF3G9S0qCrLra6q8V2Z2O7bfKXy59hzlj3+G61qQV91OzYB8BThSYnh7qM 9j9e2zhrdIntNklUIaCf9lMV+Bw2vSram+i9VNXafQZGQsF4ctB/MQPwJcueDQOaC4VO 1pZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=NWG9grRsxUmH4u+WMkh8hg9iSj2KGxYmj7m4vuDxpFE=; b=z7lDMZAEBoyuWHZ7RlwIeVsn+0J4EYNoaMoaiXfNae6A740w/IpyFRPbTH5gzoG/Gl AAw+L9JGGNQ6es8R88k+m7MGG0Bo4T9p2e5yMSkm8SitIbMy95GRpiH862wGsC8opZRb Xk88YoI3axAFJPNwhPB1YJFlibmgHENXjceY1LHOocVw1hu72UFDEGtjISkPR0fjstw4 9ROMR5+hIsMRJZMr8ExRUUhhGjsFXSDpS9dMAwq3cYgUf2uJTJH7J5emFieZzblqJSpm 4xa2AB5YrLLYkI2LI2lSCWg0zEKxrPRrNPlTabf3kpawRL1sgiOYWS70/PZ59EjzP+uW Wc+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cUFt+sLL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g2-v6si24706960plq.242.2018.09.20.12.19.01; Thu, 20 Sep 2018 12:19:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cUFt+sLL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388952AbeIUBD6 (ORCPT + 32 others); Thu, 20 Sep 2018 21:03:58 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:47007 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388926AbeIUBD5 (ORCPT ); Thu, 20 Sep 2018 21:03:57 -0400 Received: by mail-pf1-f196.google.com with SMTP id u24-v6so4806723pfn.13 for ; Thu, 20 Sep 2018 12:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NWG9grRsxUmH4u+WMkh8hg9iSj2KGxYmj7m4vuDxpFE=; b=cUFt+sLLeLDzFjkfrELI2DxG3Ni+wGyqlJLpVTmiATnZmw4QiDHm2G0MpObVzvHwiu /4i7LjIA/354MOEs/ss6xE5EcPYKnL/96RIb09lZgBi7vKBBBGa+HMZW77SAq5iqGBTF ccsg3JVcdxaVy9fPBwOHbzZpmJhcioB68EtPU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NWG9grRsxUmH4u+WMkh8hg9iSj2KGxYmj7m4vuDxpFE=; b=CBfw1jZKsJlK9oM48I8YlWbH7iJqO4LJEfEa1J4w3Qkh1ZxDgtEZ7dqdNDdY/HvMdx wBKZQoppwyOLXXu4JpzfBjN4SDHEaKCVTOFqIbAcDiu8TTOq1bHHxxlmTNXyWY9BapRN Q7wLGSU2PEvy2aepJf0stW0iqZt/c1vh31iTgSdzm89jHgm0h6pKHYTNylYuo8IJQ/jo PISANHuyxe4ewGne4c1ASAUJAWHzaTlwE8uD5oqvAIFOfUzgAKjQYZVcOHO6Vyqgqo9n HvEZdE8e02k4GBdZtPiog0WEHmUybuce54CWRj5NkE8j7xtGj3NgiXRyjs+MF+HpHhvK JDgQ== X-Gm-Message-State: APzg51Ac5ukum9ZQRkIa4EY1cJGvgZF19j7/eX7eeHNMy63J68mqEHVm ve42OYcq3sBuGnx+TNk1aBMHeSG7u2c= X-Received: by 2002:a62:9101:: with SMTP id l1-v6mr42647547pfe.226.1537471138461; Thu, 20 Sep 2018 12:18:58 -0700 (PDT) Received: from localhost.localdomain ([209.121.128.187]) by smtp.gmail.com with ESMTPSA id k13-v6sm4424443pgf.37.2018.09.20.12.18.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Sep 2018 12:18:57 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 24/44] coresight: etb10: Splitting function etb_enable() Date: Thu, 20 Sep 2018 13:17:59 -0600 Message-Id: <1537471099-19781-25-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537471099-19781-1-git-send-email-mathieu.poirier@linaro.org> References: <1537471099-19781-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Up until now the relative simplicity of enabling the ETB made it possible to accommodate processing for both sysFS and perf methods. But work on claimtags and CPU-wide trace scenarios is adding some complexity, making the current code messy and hard to maintain. As such follow what has been done for ETF and ETR components and split function etb_enable() so that processing for both API can be done cleanly. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 73 +++++++++++++++++++-------- 1 file changed, 52 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 69287163ce4e..08fa660098f8 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -134,7 +134,7 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) +static int etb_enable_sysfs(struct coresight_device *csdev) { int ret = 0; unsigned long flags; @@ -142,48 +142,79 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) spin_lock_irqsave(&drvdata->spinlock, flags); - /* - * When accessing from Perf, a HW buffer can be handled - * by a single trace entity. In sysFS mode many tracers - * can be logging to the same HW buffer. - */ + /* Don't messup with perf sessions. */ if (drvdata->mode == CS_MODE_PERF) { ret = -EBUSY; goto out; } - /* Don't let perf disturb sysFS sessions */ - if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_PERF) { - ret = -EBUSY; + /* Nothing to do, the tracer is already enabled. */ + if (drvdata->mode == CS_MODE_SYSFS) goto out; - } - /* Nothing to do, the tracer is already enabled. */ - if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_SYSFS) + drvdata->mode = CS_MODE_SYSFS; + etb_enable_hw(drvdata); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; +} + +static int etb_enable_perf(struct coresight_device *csdev, void *data) +{ + int ret = 0; + unsigned long flags; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* No need to continue if the component is already in use. */ + if (drvdata->mode != CS_MODE_DISABLED) { + ret = -EBUSY; goto out; + } /* * We don't have an internal state to clean up if we fail to setup * the perf buffer. So we can perform the step before we turn the * ETB on and leave without cleaning up. */ - if (mode == CS_MODE_PERF) { - ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); - if (ret) - goto out; - } + ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); + if (ret) + goto out; - drvdata->mode = mode; + drvdata->mode = CS_MODE_PERF; etb_enable_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); - - if (!ret) - dev_dbg(drvdata->dev, "ETB enabled\n"); return ret; } +static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + int ret; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + switch (mode) { + case CS_MODE_SYSFS: + ret = etb_enable_sysfs(csdev); + break; + case CS_MODE_PERF: + ret = etb_enable_perf(csdev, data); + break; + default: + ret = -EINVAL; + break; + } + + if (ret) + return ret; + + dev_dbg(drvdata->dev, "ETB enabled\n"); + return 0; +} + static void etb_disable_hw(struct etb_drvdata *drvdata) { u32 ffcr;