From patchwork Wed Sep 5 09:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 145979 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4719365ljw; Wed, 5 Sep 2018 02:49:56 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda/UIUhheIpT/qUQY7dqrKeZvBDcEldokAC6jmpMHYMIRxJMzFkPR8KKBxpcyLQrDr86Omw X-Received: by 2002:a63:4106:: with SMTP id o6-v6mr24158930pga.80.1536140996265; Wed, 05 Sep 2018 02:49:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536140996; cv=none; d=google.com; s=arc-20160816; b=pvhSGeSW8MkX6W2Zz1aUYkotdElXyopOEubVR6bdOctEr5DoKi9OY2dKMj5h0BCd8o gCn9/Yv7N/DsjfFNxLjTW9WTYVKAauqzVzp+MPppTGn6UW2vvKD+S7hOC/LOnti/K1qB esBRUpS5ipSjncmeB8YGd1FfVBXevOMW2MtUUklAU8ulpjR/+Rb7gpKGJFjLDfQErG7b aCV9gjVu6IkEDhBc4dqJKLV1mJve6sZ6kKDhhKyDSGkWuO4fjNZ6aSL5LxSjtl3b515M 8ODsIktg/XUYfH3SxNodsGkfbyvruR/wBgciLgXab7g9e05Uj8GT8dCCMmiOWFmHWcc6 mexQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=qn6UpFmXCudWZSLClz63rFlAuYledj5I/oi/6T0TT4Q=; b=Dsxtz2LYrub9UfIsQP/ByOX5IgpYbx84VZH1iM23otzzMXQ7br0vgW4Tjlc6KB9RL7 afxTACI+AguI8Ag6bLBTHHKtC4Tr4jrXplX7MxWGL8YMjw9Vd3Zps8GNjEqnzkBz/S4B jdU3OS9MuPg1LrS3g4kzWRUz9maJcMLU/y8nl5OQbcFo6FzZ81E0aoYT49O1WDFsHWL6 dXKkHEcUQlmR0/egYGWvd4AtPIYPlA6gbfkZ1JSte6WnxcvaPgASrE+zuINh+SqdLwaj dXDUe5X4Xad9SRXA9usr1bXtEbzGX0ATpX/W+QXv5My+Yl0qqGeJARlwz160iOiZdYZ8 d+mw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g66-v6si1639344pfk.53.2018.09.05.02.49.55; Wed, 05 Sep 2018 02:49:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728109AbeIEOTT (ORCPT + 32 others); Wed, 5 Sep 2018 10:19:19 -0400 Received: from mx.socionext.com ([202.248.49.38]:54956 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726272AbeIEOTT (ORCPT ); Wed, 5 Sep 2018 10:19:19 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 05 Sep 2018 18:49:52 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 33D431800E0; Wed, 5 Sep 2018 18:49:52 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 5 Sep 2018 18:49:52 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 765761A16F7; Wed, 5 Sep 2018 18:49:51 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 1/2] dt-bindings: phy: add UniPhier PCIe PHY description Date: Wed, 5 Sep 2018 18:49:44 +0900 Message-Id: <1536140985-6058-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/phy/uniphier-pcie-phy.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt new file mode 100644 index 0000000..1889d3b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt @@ -0,0 +1,31 @@ +Socionext UniPhier PCIe PHY bindings + +This describes the devicetree bindings for PHY interface built into +PCIe controller implemented on Socionext UniPhier SoCs. + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY + "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY +- reg: Specifies offset and length of the register set for the device. +- #phy-cells: Must be zero. +- clocks: A phandle to the clock gate for PCIe glue layer including + this phy. +- resets: A phandle to the reset line for PCIe glue layer including + this phy. + +Optional properties: +- socionext,syscon: A phandle to system control to set configurations + for phy. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + };