From patchwork Thu Aug 30 16:15:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 145542 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp91601ljw; Thu, 30 Aug 2018 09:15:59 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda9NVU6CQqcT1uO2qWRw55t3cDS6l7dJUqqkb8hcW8O63wfNNk1lW4IwCB56lQb2SEQK6Li X-Received: by 2002:a62:1456:: with SMTP id 83-v6mr11060969pfu.50.1535645758918; Thu, 30 Aug 2018 09:15:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535645758; cv=none; d=google.com; s=arc-20160816; b=D/K4La4zKli45fDPRwVXKWCBdH+yma9gWK+Tod3F2Kxsh+UW+aE3WIqLZKPjBQxfiO KhK532HOBhSs0tFLkhn+U2EaCc1bdIlrVr+usHHC0dKX088Tf2NzLDbAPtnk0iQoRW73 fSkYje0nKS7CZxsCOKS/Qs+ZUUGN/juvmphrRJ1En/M5ztYTzw4dT2JTOqGsSfUX/UZM t7KJz0pzwI7BbOrtDsk2Doh5FI2/YV3lUGGxcDPF6er64D479iNVTxZzpMhK+q6r8IVD VS9dPmYugiebAene1NEdiC2RG6X5kL95S2oZHaiPgnFuADTTDRr1KHcp7740O5SGxoRB l78Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=ksv87UoDxthcwe7X1NoH8+m+mtxsLpbGHAdZrue+4qE=; b=WnfEK2s/StdO+WFdQG0m3yCx0HNm9AujuxIFZ9WuINh9EHK8YG28ok+wDN0jO6WdO1 /Ucpqu/+7pMHNzAkw3IOdWCd5cb8qaICOZw101z09UH6V4v1MgQlfzsRG19whwj8BuxA 3O7fsOUzHT/4W5IZpNGw1evF0+TXvWqECvKxqRoe+t4LBBS+ODCNceU7QQ5UT84E1rGc 8X/yItmm3YnBLQBRAi7DNQIhXIR7+8p/LE67zMQcdn/xZ+ljYTxLBI+gVtk/vq+eGFqB CuIS2ZCxoJfMG+fe0MJGTZvPGrqPO6p5+6HzmRSgiuKg9n46XQro3+FqAZeGopgZJKkk 9xBQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id go14si6856704plb.458.2018.08.30.09.15.58; Thu, 30 Aug 2018 09:15:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727725AbeH3USn (ORCPT + 32 others); Thu, 30 Aug 2018 16:18:43 -0400 Received: from foss.arm.com ([217.140.101.70]:44902 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727659AbeH3USn (ORCPT ); Thu, 30 Aug 2018 16:18:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 178FE1BB2; Thu, 30 Aug 2018 09:15:50 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DD25C3F994; Thu, 30 Aug 2018 09:15:49 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id B45241AE3A87; Thu, 30 Aug 2018 17:16:01 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, benh@au1.ibm.com, torvalds@linux-foundation.org, npiggin@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, Will Deacon Subject: [PATCH 10/12] arm64: tlb: Adjust stride and type of TLBI according to mmu_gather Date: Thu, 30 Aug 2018 17:15:44 +0100 Message-Id: <1535645747-9823-11-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1535645747-9823-1-git-send-email-will.deacon@arm.com> References: <1535645747-9823-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the core mmu_gather code keeps track of both the levels of page table cleared and also whether or not these entries correspond to intermediate entries, we can use this in our tlb_flush() callback to reduce the number of invalidations we issue as well as their scope. Signed-off-by: Will Deacon --- arch/arm64/include/asm/tlb.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h index bd00017d529a..b078fdec10d5 100644 --- a/arch/arm64/include/asm/tlb.h +++ b/arch/arm64/include/asm/tlb.h @@ -34,20 +34,21 @@ static void tlb_flush(struct mmu_gather *tlb); static inline void tlb_flush(struct mmu_gather *tlb) { struct vm_area_struct vma = TLB_FLUSH_VMA(tlb->mm, 0); + bool last_level = !tlb->freed_tables; + unsigned long stride = tlb_get_unmap_size(tlb); /* - * The ASID allocator will either invalidate the ASID or mark - * it as used. + * If we're tearing down the address space then we only care about + * invalidating the walk-cache, since the ASID allocator won't + * reallocate our ASID without invalidating the entire TLB. */ - if (tlb->fullmm) + if (tlb->fullmm) { + if (!last_level) + flush_tlb_mm(tlb->mm); return; + } - /* - * The intermediate page table levels are already handled by - * the __(pte|pmd|pud)_free_tlb() functions, so last level - * TLBI is sufficient here. - */ - __flush_tlb_range(&vma, tlb->start, tlb->end, PAGE_SIZE, true); + __flush_tlb_range(&vma, tlb->start, tlb->end, stride, last_level); } static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,