From patchwork Wed Jul 18 14:14:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142285 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594445ljj; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeqo9G84iiov3Ao6ALIh3HD0+FSKE/gpjohVVKQepiKC6fbAlbbCDKz6vllAWPMxTdAr4Av X-Received: by 2002:a63:d916:: with SMTP id r22-v6mr5844900pgg.381.1531923403242; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923403; cv=none; d=google.com; s=arc-20160816; b=AHMJY+oAWV1Zs44Qt3KvA7PyBjyS9/iGX5VS6FBp8H6mxKZ1Mj7EykHiyKZf31ZGr2 aRYmkegBedWK4578jfcfxZMWfOmpCKLYmM/ritAgf9GB2VMoPfN77HpGOVdX4revZTAg F78EvEUHZFVXIbMq8Km1gooH9S+hor4CvPQZRgX7CULcnIarVfR1UquyqGWE7tvBeQbp tSNlBp7LPdiw6XOTYSBDH05aR3+tEY4pR1uyQKYn6EhPJVAVfPlEAI5Ny7O8bxR0Cso1 dXCeDfYaAhRkiXokvypYxgL8xJOxwEFp8Wo50eS4jVcyURTmdrIDujUADs3ZcP35keuZ 1KsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=DvYSZZX4Q5baI7Ep8DxFga5tlsCAaX7KlsF33EXYC50=; b=bNgg7hAuEWTJFUm+QpMl6oBOjth9ROIZQgxH5NrnSm5HRYzWCuZp/Nv6C/y2U4T0li xTGpHlaZ2C+cMj9cZO0FQhmM0zd+JxQW1s2EH9X/DDcGRAIOBqqrRGekF3+BUDkexLAI Jv2ddk6nBI0Qgm7zxvQau2/yom9bP1of3dY0BZjej7A3mL55/rJ8ICfw75xf5pkCponp ketY+xwtOR/p5ZvJ3wBw1SCG8s+ai/MOXY/bnwV1703PBNTsZ4I36otVMLtmoBhcWA/w u4JJ5qBinHD32ekgULukcW5ZoHRNZhBu5GihsS9A5muaEuUlfGyO7deWTv88TPyLTe3s AQag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j61-v6si3351881plb.68.2018.07.18.07.16.42; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731473AbeGROyr (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:47 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9697 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730987AbeGROy3 (ORCPT ); Wed, 18 Jul 2018 10:54:29 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 272E06796FA1F; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:57 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 6/9] scsi: hisi_sas: Implement handlers of PCIe FLR for v3 hw Date: Wed, 18 Jul 2018 22:14:30 +0800 Message-ID: <1531923273-193768-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan This patch implements handlers of PCIe FLR for v3 hw, reset_prepare() and reset_done(). User can issue FLR through sysfs interface, as v3 hw support PCIe FLR. Then if we don't implement these two handlers, our SAS controller will not work after executing FLR. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3577843..3d20fcf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -2465,6 +2465,41 @@ static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) return PCI_ERS_RESULT_DISCONNECT; } +static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) +{ + struct sas_ha_struct *sha = pci_get_drvdata(pdev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + struct device *dev = hisi_hba->dev; + int rc; + + dev_info(dev, "FLR prepare\n"); + set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); + hisi_sas_controller_reset_prepare(hisi_hba); + + rc = disable_host_v3_hw(hisi_hba); + if (rc) + dev_err(dev, "FLR: disable host failed rc=%d\n", rc); +} + +static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) +{ + struct sas_ha_struct *sha = pci_get_drvdata(pdev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + struct device *dev = hisi_hba->dev; + int rc; + + hisi_sas_init_mem(hisi_hba); + + rc = hw_init_v3_hw(hisi_hba); + if (rc) { + dev_err(dev, "FLR: hw init failed rc=%d\n", rc); + return; + } + + hisi_sas_controller_reset_done(hisi_hba); + dev_info(dev, "FLR done\n"); +} + enum { /* instances of the controller */ hip08, @@ -2556,6 +2591,8 @@ static int hisi_sas_v3_resume(struct pci_dev *pdev) .error_detected = hisi_sas_error_detected_v3_hw, .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, .slot_reset = hisi_sas_slot_reset_v3_hw, + .reset_prepare = hisi_sas_reset_prepare_v3_hw, + .reset_done = hisi_sas_reset_done_v3_hw, }; static struct pci_driver sas_v3_pci_driver = {