From patchwork Wed Jul 18 14:14:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142281 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594038ljj; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd3XLFageW3a4lszA9K1Wfm7YX4Gvvcoxh14HVEafU/P0Q1/TupNcrj+2IpHt8pGhFnu1Et X-Received: by 2002:a63:5055:: with SMTP id q21-v6mr5730979pgl.397.1531923383041; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923383; cv=none; d=google.com; s=arc-20160816; b=fD5VS0dYW0ul6rhdDkP8HQe/dlKYy3bK5ycWOBlFa+2o0aSJRyM7CyLbNDBxF4Q14e 61bAp6KgllEkpo2KqcUmxYrYeHy5M3LSl9lxupOGw1c694PF84n5wJv6mqW9hU7bNVul b/BhetgQUX9QB05kfQ6FgErngq1vwfgoUrU/reieFGoE0iJZMLvztSNwI7uODX4zZgPo e56K8cMXe7Inmq6wUj0nDVIUna7LCLHjONKYF89k7R0rUOc7bVC86T0xpOFpYpKb903q Udk96d/xVG18IPYQuIvn//ZaxodXrUz2l9+0i0mErIEpMkrhuhLtQqkfgH+tKBsUq/Bf iPuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=XH51d3aK3bsowjdGkeYn800p4cgLkwIT+0dIkm0NY6M=; b=z0lvUKODxLTuh6yQrSFnl4Vvt9m36umwAjgB5vIRRwvEjwNh3nX1nH/ykWdYH2lA/D ddRnACGtbdqIz1T+hvuag4wekaru/6GKpj2/1wx0WkeVdk4mF+aRgcZjbcFrDpV4D/Fh B1gz3BwvcouMgj5d3XFQ3qsViw55P8nbmmZYTpofD1TYuVle5q0iekdcvMI3uZn9a2oo bQO2jRXoYkwKNp7hqmHRr0Q2C6kNjjT653+r4rQ1OwUqa1fKHxxnfGTqwj27dr72qNez N9QIjLKns5w8dC1WRdnP/tbb394Ya0+EIVZ338/TeAlc+Qv0jV66/o6/1OgzXchXO8d1 l4Zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s11-v6si3182834plp.464.2018.07.18.07.16.22; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731262AbeGROy1 (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:27 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9695 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730869AbeGROy0 (ORCPT ); Wed, 18 Jul 2018 10:54:26 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 09F4353F9BD3E; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:56 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 3/9] scsi: hisi_sas: Fix the failure of recovering PHY from STP link timeout Date: Wed, 18 Jul 2018 22:14:27 +0800 Message-ID: <1531923273-193768-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan There is an issue that link reset can't recover PHY when STP link timeout. Because current process of enabling PHY for v3 hw will wait last transmission done. The time of one transmission depends IO size, disk model and so on. Normally, it should be shorter than 50ms. But the last transmission could be never done for some abnormal scenarios, such as STP link timeout. This patch is to fix the issue. Check PHY status after starting process of enabling PHY for 50ms. If the PHY is still active, we disable it forcibly by PHY reset. Of course, we need to clear the PHY reset bit when enable PHY. Besides, the function disable_phy_v3_hw() should not be suitable to call in interrupts for hilink bug for this 50ms delay. Then, we do link reset for hilink bug directly. The change is that we don't clear the invalid dword count register. This is better. Because we should not clear such error count while not saved. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index d7c3774..70a6aa2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -120,6 +120,8 @@ #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) #define PHY_CFG_DC_OPT_OFF 2 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) +#define PHY_CFG_PHY_RST_OFF 3 +#define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) #define PHY_CTRL (PORT_BASE + 0x14) #define PHY_CTRL_RESET_OFF 0 @@ -760,15 +762,25 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); cfg |= PHY_CFG_ENA_MSK; + cfg &= ~PHY_CFG_PHY_RST_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + u32 state; cfg &= ~PHY_CFG_ENA_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); + + mdelay(50); + + state = hisi_sas_read32(hisi_hba, PHY_STATE); + if (state & BIT(phy_no)) { + cfg |= PHY_CFG_PHY_RST_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); + } } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) @@ -1385,8 +1397,6 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); } - hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); - if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && (pci_dev->revision == 0x20)) { u32 reg_value; @@ -1396,15 +1406,11 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) HILINK_ERR_DFX, reg_value, !((reg_value >> 8) & BIT(phy_no)), 1000, 10000); - if (rc) { - disable_phy_v3_hw(hisi_hba, phy_no); - hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, - BIT(CHL_INT2_RX_INVLD_DW_OFF)); - hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); - mdelay(1); - enable_phy_v3_hw(hisi_hba, phy_no); - } + if (rc) + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); } static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)