From patchwork Wed Jul 18 14:14:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142288 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594770ljj; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) X-Google-Smtp-Source: AAOMgpegBz++bG8RaRX97ne8Sx+N3YGwx6Yg8dwpOgurbs1f/Q4VDpCJTjtj2cVpSrFg+2w8HA3F X-Received: by 2002:a62:a05:: with SMTP id s5-v6mr5361069pfi.147.1531923420515; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923420; cv=none; d=google.com; s=arc-20160816; b=FxcRxBpeq9BI2AmUq3CZiENjLEPIu8S7xlzTwMpM4n9DJgN+R6u98Jz4JyJj2uajIm pxaBG6PRJCqD6olNNCYkVdtxGq9Anh5TR/6sYDKKto1OFaXJSVx/QrwgDeNjn36UVz+h C5pMzD2g8/4eXGdMi6YeLidwdKe3w7jK/vniMjVnSzr/pxSMWb3neY+uBzsyIPTK+Bqk Us7lfEBowxDE3MzuLAGJnOKfMWwxrOuvX8sqQN0u18VqVrCiRR8awgA9z3YWhq9Kiw9w vQJuaE4fKFOJJV0PokK7SaPSG3Etl6vZ0wHwaNX2s3mp7+L37SmQsvAa0owaN6CuqMh2 CvJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/GPmg1Kl8k3s5K+o69nOxLlQCd1vHPI9xsxXkygilx8=; b=gihpnudV09WsUu5Pv2KsgupfeQlUCL5yNcBNwM4yvoEjFoxJaMje1NrsdLnHDuajGu HEFNLr4WCyfqC4X4t3QjQcfeoEi3jLG/QdmxQbqNoDHSQaSHGvrwUDWhKsu65qIS9iII Z6TZ6chOCvevn50oHdF1zJ0OnV6JTQf6myLjSIgusdM2Sd0kAF9kTybuvkWUHpqlHQnI +UCpjGjyyiDv6TYvI3qUS3DM2DUPSULivmgRpZFCwYqGr5e5s39T9ODfbMCg/qvRJ5f2 aXJ1ZHuZyD79R5DZSAK4hIsi1cbjUiZ9nQHnlruPUfFnDTs97X5Mp77ENrGKjtz/lh4C RdHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3-v6si3501710plh.34.2018.07.18.07.17.00; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731562AbeGROzF (ORCPT + 31 others); Wed, 18 Jul 2018 10:55:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9694 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730982AbeGROy1 (ORCPT ); Wed, 18 Jul 2018 10:54:27 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id EE7F3ADD7473F; Wed, 18 Jul 2018 22:16:03 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:55 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 2/9] scsi: hisi_sas: tidy channel interrupt handler for v3 hw Date: Wed, 18 Jul 2018 22:14:26 +0800 Message-ID: <1531923273-193768-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The ISR of channel interrupt of v3 hw is a little long and messy. This patch tidies it by relocating CHL_INT1 and CHL_INT2 handling to new function separately. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 156 ++++++++++++++++----------------- 1 file changed, 78 insertions(+), 78 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4b7688a..d7c3774 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1333,11 +1333,83 @@ static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) }, }; -static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) +static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { - struct hisi_hba *hisi_hba = p; + u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); struct device *dev = hisi_hba->dev; + int i; + + irq_value &= ~irq_msk; + if (!irq_value) + return; + + for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { + const struct hisi_sas_hw_error *error = &port_axi_error[i]; + + if (!(irq_value & error->irq_msk)) + continue; + + dev_err(dev, "%s error (phy%d 0x%x) found!\n", + error->msg, phy_no, irq_value); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); + } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); +} + +static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; struct pci_dev *pci_dev = hisi_hba->pci_dev; + struct device *dev = hisi_hba->dev; + + irq_value &= ~irq_msk; + if (!irq_value) + return; + + if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { + dev_warn(dev, "phy%d identify timeout\n", phy_no); + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); + } + + if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { + u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, + STP_LINK_TIMEOUT_STATE); + + dev_warn(dev, "phy%d stp link timeout (0x%x)\n", + phy_no, reg_value); + if (reg_value & BIT(4)) + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); + } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); + + if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && + (pci_dev->revision == 0x20)) { + u32 reg_value; + int rc; + + rc = hisi_sas_read32_poll_timeout_atomic( + HILINK_ERR_DFX, reg_value, + !((reg_value >> 8) & BIT(phy_no)), + 1000, 10000); + if (rc) { + disable_phy_v3_hw(hisi_hba, phy_no); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, + BIT(CHL_INT2_RX_INVLD_DW_OFF)); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + mdelay(1); + enable_phy_v3_hw(hisi_hba, phy_no); + } + } +} + +static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) +{ + struct hisi_hba *hisi_hba = p; u32 irq_msk; int phy_no = 0; @@ -1347,84 +1419,12 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) while (irq_msk) { u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); - u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT1); - u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT2); - u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT1_MSK); - u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT2_MSK); - - irq_value1 &= ~irq_msk1; - irq_value2 &= ~irq_msk2; - - if ((irq_msk & (4 << (phy_no * 4))) && - irq_value1) { - int i; - - for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { - const struct hisi_sas_hw_error *error = - &port_axi_error[i]; - - if (!(irq_value1 & error->irq_msk)) - continue; - - dev_err(dev, "%s error (phy%d 0x%x) found!\n", - error->msg, phy_no, irq_value1); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT1, irq_value1); - } - if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { - struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; - - if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { - dev_warn(dev, "phy%d identify timeout\n", - phy_no); - hisi_sas_notify_phy_event(phy, - HISI_PHYE_LINK_RESET); - - } + if (irq_msk & (4 << (phy_no * 4))) + handle_chl_int1_v3_hw(hisi_hba, phy_no); - if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { - u32 reg_value = hisi_sas_phy_read32(hisi_hba, - phy_no, STP_LINK_TIMEOUT_STATE); - - dev_warn(dev, "phy%d stp link timeout (0x%x)\n", - phy_no, reg_value); - if (reg_value & BIT(4)) - hisi_sas_notify_phy_event(phy, - HISI_PHYE_LINK_RESET); - } - - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT2, irq_value2); - - if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && - (pci_dev->revision == 0x20)) { - u32 reg_value; - int rc; - - rc = hisi_sas_read32_poll_timeout_atomic( - HILINK_ERR_DFX, reg_value, - !((reg_value >> 8) & BIT(phy_no)), - 1000, 10000); - if (rc) { - disable_phy_v3_hw(hisi_hba, phy_no); - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT2, - BIT(CHL_INT2_RX_INVLD_DW_OFF)); - hisi_sas_phy_read32(hisi_hba, phy_no, - ERR_CNT_INVLD_DW); - mdelay(1); - enable_phy_v3_hw(hisi_hba, phy_no); - } - } - } + if (irq_msk & (8 << (phy_no * 4))) + handle_chl_int2_v3_hw(hisi_hba, phy_no); if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { hisi_sas_phy_write32(hisi_hba, phy_no,