From patchwork Thu May 24 10:59:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136731 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2039354lji; Thu, 24 May 2018 03:59:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo0X4S0LiFg6f7VS9cKFxkJ2eHestilR52VQOjKnQWUQNKpepEnEp8WImbWJl4nv/bZ4AFY X-Received: by 2002:a17:902:aa4b:: with SMTP id c11-v6mr6873620plr.17.1527159567538; Thu, 24 May 2018 03:59:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159567; cv=none; d=google.com; s=arc-20160816; b=qHuSj1QHRpW9m02PNM+69qWo6Cdbvv9UoPv/5pn2gygFXjug/FxONaiFto753CYRt7 7G1ynctE5r4AAw6sCLZN98dIbWGqjHW22cFJZoE4+oAmAVzciR/LPs7IDfqaHCsqQwRY begGHWLdzd1sVJ8zcNTsHKHaLGWfeojrPZMlQUHoFmI1ETh3Rqit0H0u9uhgbtExfjc2 dsFLjRvK8kvbAUXskT9H1uJThj1TYT6+gwaeg3eObnDQ1MkEa2gtMGAUa8CRArGa3n6J sCGk5h8ZpJAnmZc1lWVuwoGNrnUg3q1kq+UiukksLWLujm/0xo1CQIHKdA4hIwePZGWK ROtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dxsWqaY+cyvP9/Wn+QoATPyiIJKTrgv/4wVaFT6fg7E=; b=tbw5KDEBrzIk58Hj03Rwjo9YxskuCBsuXSlBAvzQFo5t7iuaHPF25EA2A7bGw7m/4l gGR6YGaEw8tlUHsPGn5CVHdzuisB98g+u/I666GJuD8VUwF9VByvQ+VxqyvUqoK7t347 aGY7sqNcyNHyrN4hbEd27C6laPaUReqKdgA5mruKxr51a90Mnrhp8k2eCOO+fO7qigwx K1bMN55/p0ByJ/Y1Cq8+zjihkc3FgOYRyfyaUBzRAYE008u1uB96fCZm8adK+FDLY0NX 4fEI17K+HkpVESRETlDf1mngztnjFecTKpwjiJ43Unu39W9pyqxQYjyd0SurW0+x4mx6 vt7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d9-v6si16344978pga.192.2018.05.24.03.59.27; Thu, 24 May 2018 03:59:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032738AbeEXK7Z (ORCPT + 30 others); Thu, 24 May 2018 06:59:25 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030372AbeEXK7T (ORCPT ); Thu, 24 May 2018 06:59:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A15CE1688; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 720823F7B4; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 719121AE3856; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 3/9] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Thu, 24 May 2018 11:59:40 +0100 Message-Id: <1527159586-8578-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT and masking macros into a new header file, linux/bits.h Signed-off-by: Will Deacon --- include/linux/bitops.h | 22 +--------------------- include/linux/bits.h | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/linux/bits.h -- 2.1.4 diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..af419012d77d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); diff --git a/include/linux/bits.h b/include/linux/bits.h new file mode 100644 index 000000000000..2b7b532c1d51 --- /dev/null +++ b/include/linux/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_BITS_H +#define __LINUX_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __LINUX_BITS_H */