From patchwork Mon May 21 11:35:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Thierry X-Patchwork-Id: 136453 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp197425lji; Mon, 21 May 2018 04:35:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrvbqIwqbvM9dni9bYGs1WN3NQomRH61Qs3BNpMKsPQqzDyFHpeNFozI3N+GSh6Vf9eHayt X-Received: by 2002:a63:4004:: with SMTP id n4-v6mr15708494pga.248.1526902548017; Mon, 21 May 2018 04:35:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526902548; cv=none; d=google.com; s=arc-20160816; b=k7bNEgN6kdkia4laV5A6STMG6+hOikptXxnWtQGN/lmnFJP/W8aZKGx2kPHvR0TANS uMzJWeNe3foYBUnJSCQvnNpdj7AkvT+FT5poGrvNg2g9kTwqR7m74WlPi/24oalApOLW aBLE/NQ8zocYssK0JT5yIFoMHjmlEv0Zkpk62WKaO/EU7ipSjyLfOFEpg/Z8IVG44QD2 rTbllNYadM154ZyAtuYUPvHi1LPFV+5TkblsgDwaUQp6Fx8tyTnw2rqAq2MWrnUzCCp2 lweNSgkk2wmAoNePIHqHetSiHE/0vNHCTj5I4TMYYU3lk+XnqKkJbl0pdXOCPBPt+Cot lXig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xzfKTNrZTZNMqokOzxs0KBRl75BbbAU5Hnn3+dm56TY=; b=J0XpsGN8j1b9TvUmqlAZu88okXYcA1u0p9FVkNfEaxLS4DaVuit7HUkdNkirfQA2Er 1Km80yfIhSaSYJuHIt/qXI3Pi9PFkxl28r2/PC3B99QImJjSQjA/4qVamsd3E4LW60OS tTDkwTTqOCraDs6McOtxpS2IEDrsk4fmSu2eMBXyN42mUzDkIMgUVo3JIJfP4YxJOcQE gfibgBiEnDQTDWGw6ts0ChJbWtzFKhZgVC2uygpjgsLciEe49EBm3hemAKyzZ6Ln5GVA 8XMPWFReuIBPrYCTmyeJdR0Vkn0c0Ynx9Qw+0JjGdowWXsAnElBDMK2wU0IB3D8y50aF waIA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u6-v6si13004128pld.74.2018.05.21.04.35.47; Mon, 21 May 2018 04:35:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752844AbeEULfq (ORCPT + 29 others); Mon, 21 May 2018 07:35:46 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47556 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752707AbeEULfk (ORCPT ); Mon, 21 May 2018 07:35:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C01281529; Mon, 21 May 2018 04:35:39 -0700 (PDT) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8C75F3F25D; Mon, 21 May 2018 04:35:37 -0700 (PDT) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, joelaf@google.com, joel.opensrc@gmail.com, daniel.thompson@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry , Suzuki K Poulose Subject: [PATCH v3 1/6] arm64: cpufeature: Allow early detect of specific features Date: Mon, 21 May 2018 12:35:10 +0100 Message-Id: <1526902515-13769-2-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526902515-13769-1-git-send-email-julien.thierry@arm.com> References: <1526902515-13769-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Daniel Thompson Currently it is not possible to detect features of the boot CPU until the other CPUs have been brought up. This prevents us from reacting to features of the boot CPU until fairly late in the boot process. To solve this we allow a subset of features (that are likely to be common to all clusters) to be detected based on the boot CPU alone. Signed-off-by: Daniel Thompson [julien.thierry@arm.com: check non-boot cpu missing early features, avoid duplicates between early features and normal features] Signed-off-by: Julien Thierry Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 Reviewed-by: Suzuki K Poulose diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9d1b06d..e03e897 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1030,7 +1030,7 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, - .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT,