From patchwork Thu Apr 26 10:34:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 134473 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp2080408lji; Thu, 26 Apr 2018 03:35:31 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/uf7R0Tk+Qnvru6riYY/bVRC30zsP9nuIf2z1Gr05d8KXgqd1Qu+VxPHsKgIiP4Flri1oH X-Received: by 2002:a17:902:9a0c:: with SMTP id v12-v6mr32459367plp.162.1524738931604; Thu, 26 Apr 2018 03:35:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524738931; cv=none; d=google.com; s=arc-20160816; b=vVWdXUXrFUQzuS8lNxqYZ4IhRHtq6DTG9e47hqBRqKdTkxLOIx7DIjU7H2dRIz0Bjf r2JSUKdSBbDvoo0GqE8MbxlbLNlUNbM3MLAuLRteiZvYuJIgHfrHsiG/FciR9InbEd3c ouwhFianHI3q79FzuyxAYey+mwa9PFpfx5wxeSDKGxJx8DrGCIfzauofK1s4/b0vVTFN /qD2r10Uzd9i3hE1mRyWjSdPElkXHxsiUyi2j4ZyStGgJyzhiTazwWJPJsAiRbjcJP0L fS3Kgi/vmxJWiZtyrzD15TK1Zc2qin4/CjX3eVdBSi0rJAob6qdytFGqlBKtBFNUVSih e2bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Gd79BK1RjZEjjy2T6jUzYMNwBJjAvxevnUzM+pM9VQo=; b=tAbY84MA0I7h1gw7i4uMtieGZwInxPGWg8Tv4Se6hbRPJ4+y4JOPlsPbWa9Qu00jEy b32GJ5hKNdeu8vs43GbDflRzz81ZV84vhs7c8CqaFtTfc0eDa6cLFZUIZIN146KUQ8ky 2R2tm0SjbRdB+FpqcP0hshPvMNaJGQ8z6BEp7aOdEUyo7yNxECMH3bb3UJu8AU3GNUK+ ysNhNLli7I1dJrJhdssfZAt5WfcVIXCcBQfZEA7awB8ERa7SSjhBm+zsBKQ6HhEqXVVs tFAz1YFMMJd6mJNNDIAho25PA2sTvkSD1M4CJgQbgPlTm4g1cz/gYl/VS7f4uP35dsBY h3ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si12380800pge.639.2018.04.26.03.35.31; Thu, 26 Apr 2018 03:35:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755694AbeDZKf2 (ORCPT + 29 others); Thu, 26 Apr 2018 06:35:28 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51148 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755227AbeDZKeL (ORCPT ); Thu, 26 Apr 2018 06:34:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 890E919F6; Thu, 26 Apr 2018 03:34:10 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5AF143F5B7; Thu, 26 Apr 2018 03:34:10 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id BD8361AE51DF; Thu, 26 Apr 2018 11:34:29 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, peterz@infradead.org, mingo@kernel.org, boqun.feng@gmail.com, paulmck@linux.vnet.ibm.com, longman@redhat.com, will.deacon@arm.com Subject: [PATCH v3 12/14] locking/qspinlock: Use try_cmpxchg instead of cmpxchg when locking Date: Thu, 26 Apr 2018 11:34:26 +0100 Message-Id: <1524738868-31318-13-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1524738868-31318-1-git-send-email-will.deacon@arm.com> References: <1524738868-31318-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When reaching the head of an uncontended queue on the qspinlock slow-path, using a try_cmpxchg instead of a cmpxchg operation to transition the lock work to _Q_LOCKED_VAL generates slightly better code for x86 and pretty much identical code for arm64. Cc: Ingo Molnar Reported-by: Peter Zijlstra Signed-off-by: Will Deacon --- kernel/locking/qspinlock.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) -- 2.1.4 diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index fa5d2ab369f9..1e3ddc42135e 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -467,16 +467,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * Otherwise, we only need to grab the lock. */ - /* In the PV case we might already have _Q_LOCKED_VAL set */ - if ((val & _Q_TAIL_MASK) == tail) { - /* - * The atomic_cond_read_acquire() call above has provided the - * necessary acquire semantics required for locking. - */ - old = atomic_cmpxchg_relaxed(&lock->val, val, _Q_LOCKED_VAL); - if (old == val) - goto release; /* No contention */ - } + /* + * In the PV case we might already have _Q_LOCKED_VAL set. + * + * The atomic_cond_read_acquire() call above has provided the + * necessary acquire semantics required for locking. + */ + if (((val & _Q_TAIL_MASK) == tail) && + atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL)) + goto release; /* No contention */ /* Either somebody is queued behind us or _Q_PENDING_VAL is set */ set_locked(lock);