From patchwork Thu Apr 26 10:34:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 134472 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp2080358lji; Thu, 26 Apr 2018 03:35:28 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+aoEPS60VkNQmRXPEz/vD1LmmhPypHDImLSB5Kbfut6kpTvkajzbqg0bG1zavXgKlYSNxh X-Received: by 2002:a17:902:bf41:: with SMTP id u1-v6mr29082719pls.257.1524738928568; Thu, 26 Apr 2018 03:35:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524738928; cv=none; d=google.com; s=arc-20160816; b=n/oWBoH2jX6ziBl5QoTxr1KLJ2Dpl6uxgeBxnpe+mDFAVRR6gZrFcQK/ya2AOaN9Gj Lhfb9FudH7x2izoxCgsuIX59bYkMJIqgxmzi5sZGRN1eZcPyr9veD98R0Cfe+mvChVEG adV4rzPRo1S9ss787LP49mKAj02g9pM6GtcqTvqMfc7OGJO6PybyHv24bwtrDYKHPyfk ObqbFjy0JsauRAPGMeWrUNjwM86XNq4O30A7YzdfWMSHQ4EjW6Gav85NtcSEK/z/oYJo kMNlupOsYmLKPf8LCXiofPa4qIdO/tWVnL0dS1Mc4WktHlARtd066LkPVXYGJycxC8EM COIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=2tA+Zl24djFBobDnFPgPbgE1iwOO4fg0RFP1P3nWloM=; b=V1kJt/MFTvuMbonxHvZvxNTWtVGpChMMvF8t6YaZB0TkhccjaZVsSujJCm9JqLIMgT EaSUPflM71uyZJMMa6LqE+2HLE+1bDAp2qsuRs7Fn45vrf9F9ZDbbsJzaz4t3uyXuLui 0pt40WGrRN3Z6AGqO4tDbNvV4fOQBmBDuh4946IvrXsWGcgkob0EIQcsEuqP1Ck3HcMp wrijKMHzFAKqmwItxgIc+Uq2uXOrPHA/E++H1H5dbPh/gmhhEGAwZyvaqYxuNtp3qI+9 EHIo3+OlioKA/srWdl2ve5oxi47o+TpZzcsRqWbas24hOL4WbXUnAyy6eeAbEc2415IJ 1WwA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si12380800pge.639.2018.04.26.03.35.28; Thu, 26 Apr 2018 03:35:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755663AbeDZKf0 (ORCPT + 29 others); Thu, 26 Apr 2018 06:35:26 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51150 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755235AbeDZKeL (ORCPT ); Thu, 26 Apr 2018 06:34:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7FE1819CC; Thu, 26 Apr 2018 03:34:10 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51F8B3F5AF; Thu, 26 Apr 2018 03:34:10 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id A92981AE519F; Thu, 26 Apr 2018 11:34:29 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, peterz@infradead.org, mingo@kernel.org, boqun.feng@gmail.com, paulmck@linux.vnet.ibm.com, longman@redhat.com, will.deacon@arm.com Subject: [PATCH v3 11/14] locking/qspinlock: Elide back-to-back RELEASE operations with smp_wmb() Date: Thu, 26 Apr 2018 11:34:25 +0100 Message-Id: <1524738868-31318-12-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1524738868-31318-1-git-send-email-will.deacon@arm.com> References: <1524738868-31318-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The qspinlock slowpath must ensure that the MCS node is fully initialised before it can be reached by another other CPU. This is currently enforced by using a RELEASE operation when updating the tail and also when linking the node into the waitqueue (since the control dependency off xchg_tail is insufficient to enforce sufficient ordering -- see 95bcade33a8a ("locking/qspinlock: Ensure node is initialised before updating prev->next")). Back-to-back RELEASE operations may be expensive on some architectures, particularly those that implement them using fences under the hood. We can replace the two RELEASE operations with a single smp_wmb() fence and use RELAXED operations for the subsequent publishing of the node. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- kernel/locking/qspinlock.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 7b8c81ebb15e..fa5d2ab369f9 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -164,10 +164,10 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) { /* - * Use release semantics to make sure that the MCS node is properly - * initialized before changing the tail code. + * We can use relaxed semantics since the caller ensures that the + * MCS node is properly initialized before updating the tail. */ - return (u32)xchg_release(&lock->tail, + return (u32)xchg_relaxed(&lock->tail, tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; } @@ -212,10 +212,11 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) for (;;) { new = (val & _Q_LOCKED_PENDING_MASK) | tail; /* - * Use release semantics to make sure that the MCS node is - * properly initialized before changing the tail code. + * We can use relaxed semantics since the caller ensures that + * the MCS node is properly initialized before updating the + * tail. */ - old = atomic_cmpxchg_release(&lock->val, val, new); + old = atomic_cmpxchg_relaxed(&lock->val, val, new); if (old == val) break; @@ -388,12 +389,18 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) goto release; /* + * Ensure that the initialisation of @node is complete before we + * publish the updated tail via xchg_tail() and potentially link + * @node into the waitqueue via WRITE_ONCE(prev->next, node) below. + */ + smp_wmb(); + + /* + * Publish the updated tail. * We have already touched the queueing cacheline; don't bother with * pending stuff. * * p,*,* -> n,*,* - * - * RELEASE, such that the stores to @node must be complete. */ old = xchg_tail(lock, tail); next = NULL; @@ -405,14 +412,8 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) if (old & _Q_TAIL_MASK) { prev = decode_tail(old); - /* - * We must ensure that the stores to @node are observed before - * the write to prev->next. The address dependency from - * xchg_tail is not sufficient to ensure this because the read - * component of xchg_tail is unordered with respect to the - * initialisation of @node. - */ - smp_store_release(&prev->next, node); + /* Link @node into the waitqueue. */ + WRITE_ONCE(prev->next, node); pv_wait_node(node, prev); arch_mcs_spin_lock_contended(&node->locked);