From patchwork Thu Apr 19 07:24:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 133704 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp319221ljf; Thu, 19 Apr 2018 00:25:29 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+3IXF+/qME/PoFGO4SM5HbqTUTO2RwPg0BttClyyNbbgfMxLWbVCs1YLrd0QSlSE4OYErJ X-Received: by 2002:a17:902:9a90:: with SMTP id w16-v6mr5044971plp.390.1524122728843; Thu, 19 Apr 2018 00:25:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524122728; cv=none; d=google.com; s=arc-20160816; b=pWw4CtxljYHgOJCfNKAyXHwVCztaISXSQHdYzutbgP+pUxSrKgq9VXXOVeoEUvt5aP UMpRxrgV4mWNLACEcosv+ypHGSVqRQi6mp97ECZ+IOp7GwTihADwAQ+1NIP1fFKQir9R QJQXVjHbXAWarB0PYAPXvnViJnsXc/P515OMLTUY/MCrf9g2iTPmKoG3z83HecqHzwFU tHzsvEwl4pcTp/Hw9QudRl+TOUJD2Q4MCzaYbcD3L9YUUoCCH1kYUoGAftwing79OsOL O/PL8oLOHAPgWEX/cmauCpLCf6jlMTl2xnGZBNortf9FXQjhzfCEC8+KsIsJWbxUSR+B L5Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=zp4+3x2nL2c1tYuy7GSNgjIg2fIcl3VirGqS5hnEo7o=; b=fUSgIYIcIxInPiLMla8qRYZ53cKFU2FpHoxewrTgIZTTzfHffF8Z5tMQp7/EnE+KYM 6Y6pjy4UJ+KCCrtiUAA0pZzkItwHSEKpBTfUN69EW36KtHkfqkwr3+F0CBqTsq78pawb ZrCGmjzGGy6sQsc++nZzB9CR5gKrIcyV1O+3z9t3V1YN6wOFQ4fo29D9ntwAS9IW1IMt TqIigm9p0t7rO8I16tRG0kNM6rFUb+9a+Enw2DEH8qwRKraHhTk50kveHohBAn5dOAEt stGFUYiLfEbGGQgWpMvsa2Wy4iHD6ph0jy1Op7LwSKvCKpfcoviiC0tHFVRcfEi1KrfY olcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c26si2800900pfh.215.2018.04.19.00.25.28; Thu, 19 Apr 2018 00:25:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752671AbeDSHZZ (ORCPT + 29 others); Thu, 19 Apr 2018 03:25:25 -0400 Received: from mx.socionext.com ([202.248.49.38]:32904 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752273AbeDSHZL (ORCPT ); Thu, 19 Apr 2018 03:25:11 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Apr 2018 16:25:10 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 3F86C180B67; Thu, 19 Apr 2018 16:25:10 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 19 Apr 2018 16:25:10 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 828AB1A1279; Thu, 19 Apr 2018 16:25:08 +0900 (JST) From: Kunihiko Hayashi To: David Miller , netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masahiro Yamada , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH net-next v2 3/3] net: ethernet: ave: add support for phy-mode setting of system controller Date: Thu, 19 Apr 2018 16:24:55 +0900 Message-Id: <1524122695-19597-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524122695-19597-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1524122695-19597-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for specifying system controller that configures phy-mode setting. According to the DT property "phy-mode", it's necessary to configure the controller, which is used to choose the settings of the MAC suitable, for example, mdio pin connections, internal clocks, and so on. Supported phy-modes are SoC-dependent. The driver allows phy-mode to set "internal" if the SoC has a built-in PHY, and {"mii", "rmii", "rgmii"} if the SoC supports each mode. So we have to check whether the phy-mode is valid or not. This adds the following features for each SoC: - check whether the SoC supports the specified phy-mode - configure the controller accroding to phy-mode The DT property accepts one argument to distinguish them for multiple MAC instances. ethernet@65000000 { ... socionext,syscon-phy-mode = <&soc_glue 0>; }; ethernet@65200000 { ... socionext,syscon-phy-mode = <&soc_glue 1>; }; Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada --- drivers/net/ethernet/socionext/Kconfig | 2 + drivers/net/ethernet/socionext/sni_ave.c | 150 ++++++++++++++++++++++++++++--- 2 files changed, 140 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/socionext/Kconfig b/drivers/net/ethernet/socionext/Kconfig index 6bcfe27..b80048c 100644 --- a/drivers/net/ethernet/socionext/Kconfig +++ b/drivers/net/ethernet/socionext/Kconfig @@ -14,6 +14,8 @@ if NET_VENDOR_SOCIONEXT config SNI_AVE tristate "Socionext AVE ethernet support" depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + depends on HAS_IOMEM + select MFD_SYSCON select PHYLIB ---help--- Driver for gigabit ethernet MACs, called AVE, in the diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c index 52940bd..f7eccee 100644 --- a/drivers/net/ethernet/socionext/sni_ave.c +++ b/drivers/net/ethernet/socionext/sni_ave.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -197,6 +199,11 @@ #define AVE_INTM_COUNT 20 #define AVE_FORCE_TXINTCNT 1 +/* SG */ +#define SG_ETPINMODE 0x540 +#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ +#define SG_ETPINMODE_RMII(ins) BIT(ins) + #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) #define AVE_MAX_CLKS 4 @@ -228,12 +235,6 @@ struct ave_desc_info { struct ave_desc *desc; /* skb info related descriptor */ }; -struct ave_soc_data { - bool is_desc_64bit; - const char *clock_names[AVE_MAX_CLKS]; - const char *reset_names[AVE_MAX_RSTS]; -}; - struct ave_stats { struct u64_stats_sync syncp; u64 packets; @@ -257,6 +258,9 @@ struct ave_private { phy_interface_t phy_mode; struct phy_device *phydev; struct mii_bus *mdio; + struct regmap *regmap; + unsigned int pinmode_mask; + unsigned int pinmode_val; /* stats */ struct ave_stats stats_rx; @@ -279,6 +283,14 @@ struct ave_private { const struct ave_soc_data *data; }; +struct ave_soc_data { + bool is_desc_64bit; + const char *clock_names[AVE_MAX_CLKS]; + const char *reset_names[AVE_MAX_RSTS]; + int (*get_pinmode)(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg); +}; + static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry, int offset) { @@ -1179,6 +1191,11 @@ static int ave_init(struct net_device *ndev) } } + ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, + priv->pinmode_mask, priv->pinmode_val); + if (ret) + return ret; + ave_global_reset(ndev); mdio_np = of_get_child_by_name(np, "mdio"); @@ -1537,6 +1554,7 @@ static int ave_probe(struct platform_device *pdev) const struct ave_soc_data *data; struct device *dev = &pdev->dev; char buf[ETHTOOL_FWVERS_LEN]; + struct of_phandle_args args; phy_interface_t phy_mode; struct ave_private *priv; struct net_device *ndev; @@ -1559,12 +1577,6 @@ static int ave_probe(struct platform_device *pdev) dev_err(dev, "phy-mode not found\n"); return -EINVAL; } - if ((!phy_interface_mode_is_rgmii(phy_mode)) && - phy_mode != PHY_INTERFACE_MODE_RMII && - phy_mode != PHY_INTERFACE_MODE_MII) { - dev_err(dev, "phy-mode is invalid\n"); - return -EINVAL; - } irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -1656,6 +1668,26 @@ static int ave_probe(struct platform_device *pdev) priv->nrsts++; } + ret = of_parse_phandle_with_fixed_args(np, + "socionext,syscon-phy-mode", + 1, 0, &args); + if (ret) { + netdev_err(ndev, "can't get syscon-phy-mode property\n"); + goto out_free_netdev; + } + priv->regmap = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(priv->regmap)) { + netdev_err(ndev, "can't map syscon-phy-mode\n"); + ret = PTR_ERR(priv->regmap); + goto out_free_netdev; + } + ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); + if (ret) { + netdev_err(ndev, "invalid phy-mode setting\n"); + goto out_free_netdev; + } + priv->mdio = devm_mdiobus_alloc(dev); if (!priv->mdio) { ret = -ENOMEM; @@ -1715,6 +1747,95 @@ static int ave_remove(struct platform_device *pdev) return 0; } +static int ave_pro4_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_ld11_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + priv->pinmode_val = 0; + break; + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_ld20_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_pxs3_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 1) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(arg); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(arg); + break; + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct ave_soc_data ave_pro4_data = { .is_desc_64bit = false, .clock_names = { @@ -1723,6 +1844,7 @@ static const struct ave_soc_data ave_pro4_data = { .reset_names = { "gio", "ether", }, + .get_pinmode = ave_pro4_get_pinmode, }; static const struct ave_soc_data ave_pxs2_data = { @@ -1733,6 +1855,7 @@ static const struct ave_soc_data ave_pxs2_data = { .reset_names = { "ether", }, + .get_pinmode = ave_pro4_get_pinmode, }; static const struct ave_soc_data ave_ld11_data = { @@ -1743,6 +1866,7 @@ static const struct ave_soc_data ave_ld11_data = { .reset_names = { "ether", }, + .get_pinmode = ave_ld11_get_pinmode, }; static const struct ave_soc_data ave_ld20_data = { @@ -1753,6 +1877,7 @@ static const struct ave_soc_data ave_ld20_data = { .reset_names = { "ether", }, + .get_pinmode = ave_ld20_get_pinmode, }; static const struct ave_soc_data ave_pxs3_data = { @@ -1763,6 +1888,7 @@ static const struct ave_soc_data ave_pxs3_data = { .reset_names = { "ether", }, + .get_pinmode = ave_pxs3_get_pinmode, }; static const struct of_device_id of_ave_match[] = {