From patchwork Wed Apr 11 18:01:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 133169 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp897959ljb; Wed, 11 Apr 2018 11:04:10 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+3uBlBdhYyvKLwL1OAlR8m9E7LpU+c5zhN6ODrthLDQjpP94zl1Cd0iA+Bap1ocTJPxPoH X-Received: by 2002:a17:902:3381:: with SMTP id b1-v6mr6144659plc.214.1523469850177; Wed, 11 Apr 2018 11:04:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523469850; cv=none; d=google.com; s=arc-20160816; b=eOd9vnMzoF2AjL9YasPz8MTpWyZT9fwTyEPHQJ8QYwyzbZKaaAD3myn7NntyWr7pGa CQumlzzHkh4XfxZCLYTs+LZ14xwzs5MtpBpUAW3cC/vxpQh9+ZJVYC5lYo2lxo+2tISP w4T8GzC8suoyjCmaZb6JBEXHAbmFcJlf4Rt8b8ttbjvEsb8ctTU9ZlCdlY044VzMoeRs 2ceq5h7jI3XW9apzAeF2dHfayndyBJRIxsL34pOdg008B7AIO3EOJqdxtWnQ7Eq+0Xv2 vNv4nsk7yrXb/DNNtzjMFzJiaUBOYHRitZDCoyIQOO8lP4GiiJhQ/l3gJRE25JiwHcHx rNXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=2tA+Zl24djFBobDnFPgPbgE1iwOO4fg0RFP1P3nWloM=; b=mTcHhuS/MZ10wR2RdYXmkD2C8KPfVSOHURy7gPUAGxtH8ABENq5x0yBC7yBnaBvhWe DKtJeE2poVoJ5IFIjspnri0lBCdEofRlvFBPldASiOQGQxvjTNsjKn67Mzz67w3wBmNd DjwOSsNtnosXT2gl3/SYEXSjqvtGMmD9cuRHbse8iEuq+QHmV/o81+a0qIKujSD7jlv3 yESJAPoawCyZuRp6V2KqBhcrCw/XjMyRDLwkPiULbWHPt+0JOAtiLBh5vv/DtrzBimD2 MyTe0gFKNirE/RWMoIAFoShI1EMb6Zhfevnhi2x52X2C4Fy7FV2EWXTPfwtkhkA0Lyo+ 6CzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si1074288pgr.411.2018.04.11.11.04.09; Wed, 11 Apr 2018 11:04:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754055AbeDKSCx (ORCPT + 29 others); Wed, 11 Apr 2018 14:02:53 -0400 Received: from foss.arm.com ([217.140.101.70]:52154 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752664AbeDKSBH (ORCPT ); Wed, 11 Apr 2018 14:01:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4548C16A3; Wed, 11 Apr 2018 11:01:07 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 158DE3F5B1; Wed, 11 Apr 2018 11:01:07 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 03C581AE55D7; Wed, 11 Apr 2018 19:01:21 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, peterz@infradead.org, mingo@kernel.org, boqun.feng@gmail.com, paulmck@linux.vnet.ibm.com, longman@redhat.com, Will Deacon Subject: [PATCH v2 11/13] locking/qspinlock: Elide back-to-back RELEASE operations with smp_wmb() Date: Wed, 11 Apr 2018 19:01:18 +0100 Message-Id: <1523469680-17699-12-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1523469680-17699-1-git-send-email-will.deacon@arm.com> References: <1523469680-17699-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The qspinlock slowpath must ensure that the MCS node is fully initialised before it can be reached by another other CPU. This is currently enforced by using a RELEASE operation when updating the tail and also when linking the node into the waitqueue (since the control dependency off xchg_tail is insufficient to enforce sufficient ordering -- see 95bcade33a8a ("locking/qspinlock: Ensure node is initialised before updating prev->next")). Back-to-back RELEASE operations may be expensive on some architectures, particularly those that implement them using fences under the hood. We can replace the two RELEASE operations with a single smp_wmb() fence and use RELAXED operations for the subsequent publishing of the node. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- kernel/locking/qspinlock.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 7b8c81ebb15e..fa5d2ab369f9 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -164,10 +164,10 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) { /* - * Use release semantics to make sure that the MCS node is properly - * initialized before changing the tail code. + * We can use relaxed semantics since the caller ensures that the + * MCS node is properly initialized before updating the tail. */ - return (u32)xchg_release(&lock->tail, + return (u32)xchg_relaxed(&lock->tail, tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; } @@ -212,10 +212,11 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) for (;;) { new = (val & _Q_LOCKED_PENDING_MASK) | tail; /* - * Use release semantics to make sure that the MCS node is - * properly initialized before changing the tail code. + * We can use relaxed semantics since the caller ensures that + * the MCS node is properly initialized before updating the + * tail. */ - old = atomic_cmpxchg_release(&lock->val, val, new); + old = atomic_cmpxchg_relaxed(&lock->val, val, new); if (old == val) break; @@ -388,12 +389,18 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) goto release; /* + * Ensure that the initialisation of @node is complete before we + * publish the updated tail via xchg_tail() and potentially link + * @node into the waitqueue via WRITE_ONCE(prev->next, node) below. + */ + smp_wmb(); + + /* + * Publish the updated tail. * We have already touched the queueing cacheline; don't bother with * pending stuff. * * p,*,* -> n,*,* - * - * RELEASE, such that the stores to @node must be complete. */ old = xchg_tail(lock, tail); next = NULL; @@ -405,14 +412,8 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) if (old & _Q_TAIL_MASK) { prev = decode_tail(old); - /* - * We must ensure that the stores to @node are observed before - * the write to prev->next. The address dependency from - * xchg_tail is not sufficient to ensure this because the read - * component of xchg_tail is unordered with respect to the - * initialisation of @node. - */ - smp_store_release(&prev->next, node); + /* Link @node into the waitqueue. */ + WRITE_ONCE(prev->next, node); pv_wait_node(node, prev); arch_mcs_spin_lock_contended(&node->locked);