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[209.132.180.67]) by mx.google.com with ESMTP id q12-v6si531435pll.419.2018.04.03.06.02.01; Tue, 03 Apr 2018 06:02:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f7W3MHJd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932275AbeDCNB7 (ORCPT + 29 others); Tue, 3 Apr 2018 09:01:59 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35683 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932130AbeDCNBz (ORCPT ); Tue, 3 Apr 2018 09:01:55 -0400 Received: by mail-wm0-f66.google.com with SMTP id r82so35351870wme.0 for ; Tue, 03 Apr 2018 06:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3or9WHaf3weCMh0s/TeUuUAqNTACQYV2iH/baDgnhuU=; b=f7W3MHJdOVAyDc8tu8r5fJiK6O4LKcWp+OJe7rR0iozAYokyBFaTH6Ob3UIZlB1TMZ qeoW3FfSsa0xUnpUavMVNQR0bGQEu1k8fj+uMK6OoE5fjZSMmWn75BHaZNwZZgrbJ0ev OxGk4sKmVNN4N2y5833o/1ltfF+Cp6NhpOxHA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3or9WHaf3weCMh0s/TeUuUAqNTACQYV2iH/baDgnhuU=; b=gWOUibq8JGRUUVyaFgi7LGbQNHkFt5ENOnC6ud5/MoKt0lw3EbeGcR09J1ItErEdcq LJSO9dg5zNnBldALMb6JbWstKgMPxZ3jsxY2+hpViTq2Ke0KsF+D7cp/0bU0N6BG4ZEw CcO32lqyrsCJrlT19kfnX3hv9Gp9e2jRZR6mZS3Xy9UX6zhoG4V6/AACVAa43JpjxDdi HT7Pb+/vIFTghHYeltg6i629atNyEWZ9JKUJFkAd5g2Fp5AmYgAqwPpPyfGVjCFhSXwG HXJsnyn/+BB/pXpdapVSJAXwoGKKaaasFJztE4iRqN2rwA7vR6/hPU7cicBh1d1/2p4X DUeA== X-Gm-Message-State: ALQs6tCG5fC4YlJ2BnRS6m/j2JpruSn+ZBoWUgDX+7u9XCVmzeGiDCdC pesBf44R4ZYSmSaaCg2f4R0xsV2GD0Y= X-Received: by 10.28.6.14 with SMTP id 14mr3781379wmg.42.1522760513044; Tue, 03 Apr 2018 06:01:53 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c10:b60f:70d4:5b8c]) by smtp.gmail.com with ESMTPSA id j76sm857047wmd.17.2018.04.03.06.01.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Apr 2018 06:01:52 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang Subject: [PATCH 6/6] clocksource/drivers/imx-tpm: Add different counter width support Date: Tue, 3 Apr 2018 15:00:30 +0200 Message-Id: <1522760432-32048-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> References: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang Different TPM modules have different width counters which is 16-bit or 32-bit, the counter width can be read from TPM_PARAM register bit[23:16], this patch adds dynamic check for counter width to support both 16-bit and 32-bit TPM modules. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 7403e49..05d97a6 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -17,9 +17,13 @@ #include #include +#define TPM_PARAM 0x4 +#define TPM_PARAM_WIDTH_SHIFT 16 +#define TPM_PARAM_WIDTH_MASK (0xff << 16) #define TPM_SC 0x10 #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) #define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_SC_CMOD_DIV_MAX 0x7 #define TPM_SC_TOF_MASK (0x1 << 7) #define TPM_CNT 0x14 #define TPM_MOD 0x18 @@ -33,6 +37,8 @@ #define TPM_C0SC_CHF_MASK (0x1 << 7) #define TPM_C0V 0x24 +static int counter_width; +static int rating; static void __iomem *timer_base; static struct clock_event_device clockevent_tpm; @@ -85,10 +91,11 @@ static int __init tpm_clocksource_init(unsigned long rate) tpm_delay_timer.freq = rate; register_current_timer_delay(&tpm_delay_timer); - sched_clock_register(tpm_read_sched_clock, 32, rate); + sched_clock_register(tpm_read_sched_clock, counter_width, rate); return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", - rate, 200, 32, clocksource_mmio_readl_up); + rate, rating, counter_width, + clocksource_mmio_readl_up); } static int tpm_set_next_event(unsigned long delta, @@ -141,7 +148,6 @@ static struct clock_event_device clockevent_tpm = { .set_state_oneshot = tpm_set_state_oneshot, .set_next_event = tpm_set_next_event, .set_state_shutdown = tpm_set_state_shutdown, - .rating = 200, }; static int __init tpm_clockevent_init(unsigned long rate, int irq) @@ -151,10 +157,11 @@ static int __init tpm_clockevent_init(unsigned long rate, int irq) ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "i.MX7ULP TPM Timer", &clockevent_tpm); + clockevent_tpm.rating = rating; clockevent_tpm.cpumask = cpumask_of(0); clockevent_tpm.irq = irq; - clockevents_config_and_register(&clockevent_tpm, - rate, 300, 0xfffffffe); + clockevents_config_and_register(&clockevent_tpm, rate, 300, + GENMASK(counter_width - 1, 1)); return ret; } @@ -199,6 +206,11 @@ static int __init tpm_timer_init(struct device_node *np) goto err_per_clk_enable; } + counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK) + >> TPM_PARAM_WIDTH_SHIFT; + /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ + rating = counter_width == 0x20 ? 200 : 150; + /* * Initialize tpm module to a known state * 1) Counter disabled @@ -215,12 +227,17 @@ static int __init tpm_timer_init(struct device_node *np) /* CHF is W1C */ writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC); - /* increase per cnt, div 8 by default */ - writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, + /* + * increase per cnt, + * div 8 for 32-bit counter and div 128 for 16-bit counter + */ + writel(TPM_SC_CMOD_INC_PER_CNT | + (counter_width == 0x20 ? + TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX), timer_base + TPM_SC); /* set MOD register to maximum for free running mode */ - writel(0xffffffff, timer_base + TPM_MOD); + writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD); rate = clk_get_rate(per) >> 3; ret = tpm_clocksource_init(rate);