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[209.132.180.67]) by mx.google.com with ESMTP id q12-v6si531435pll.419.2018.04.03.06.01.57; Tue, 03 Apr 2018 06:01:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gZSJQ7xB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932261AbeDCNBy (ORCPT + 29 others); Tue, 3 Apr 2018 09:01:54 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45754 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932130AbeDCNBw (ORCPT ); Tue, 3 Apr 2018 09:01:52 -0400 Received: by mail-wr0-f193.google.com with SMTP id u11so18640886wri.12 for ; Tue, 03 Apr 2018 06:01:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4LPdMv2rGw8Z2OBcuXa+Ybzax2iPi2UiwBiUSSp20zI=; b=gZSJQ7xBEM5nerrg08YSel4MJ9OQs39KQUT1u1Wy24C/3HHr8qqR/P1KUIZZg06BE2 V8GSRf7lPIDl2jlDuoZObvlnJ8R37ogY20LdF0O+2iDN2jwWghxi7OrERUHnJWQ009Sk 6EJAjTVdNJ0q3zSjg5f6zq0SnzyfGTSFxmT3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4LPdMv2rGw8Z2OBcuXa+Ybzax2iPi2UiwBiUSSp20zI=; b=fU0eJE1FiQANLUcWYEw9jgkgFS8Vgdindq0umzTz+jgbSNB/boskzs3wmz0oLeL3tV qS2yDpKKvv80v3CAwR/nlzsbxtCvea3UaioZJ0HtA2BXoRIU1P8aEQS7DQJV0xDV6wXU sC69352JYjP+Q46K260xY8Xunv9dfTfWn5+CL/04r5am4AxHQo9JHlSSChnIWvuIoTgp QJz9MkcN8Q6UbsPwgqf6J/MfZ0QWGkl7yND/j6aRVJxxwB0J8E+fTkazlTRBojfP2qoi LSlDzn6YIf+D7fsBvaTYhOvP4rAC0l6ctbUD4746HS2Ai8KPkXj6RNaHWGa9RK9uBkn1 m+Nw== X-Gm-Message-State: AElRT7Hg11VtDyB9MrywCIFHioeK11AaQgdb20tkEA9klmYY1M4lpVTm E2Q7zBC4onK3rHwYy6Q/vESwOw== X-Received: by 10.223.208.133 with SMTP id y5mr9351074wrh.216.1522760511607; Tue, 03 Apr 2018 06:01:51 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c10:b60f:70d4:5b8c]) by smtp.gmail.com with ESMTPSA id j76sm857047wmd.17.2018.04.03.06.01.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Apr 2018 06:01:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang Subject: [PATCH 5/6] clocksource/drivers/imx-tpm: Correct some registers operation flow Date: Tue, 3 Apr 2018 15:00:29 +0200 Message-Id: <1522760432-32048-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> References: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang According to i.MX7ULP reference manual, TPM_SC_CPWMS can ONLY be written when counter is disabled, TPM_SC_TOF is write-1-clear, TPM_C0SC_CHF is also write-1-clear, correct these registers initialization flow; Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 3f97d49..7403e49 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -20,6 +20,7 @@ #define TPM_SC 0x10 #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) #define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_SC_TOF_MASK (0x1 << 7) #define TPM_CNT 0x14 #define TPM_MOD 0x18 #define TPM_STATUS 0x1c @@ -29,6 +30,7 @@ #define TPM_C0SC_MODE_SHIFT 2 #define TPM_C0SC_MODE_MASK 0x3c #define TPM_C0SC_MODE_SW_COMPARE 0x4 +#define TPM_C0SC_CHF_MASK (0x1 << 7) #define TPM_C0V 0x24 static void __iomem *timer_base; @@ -205,9 +207,13 @@ static int __init tpm_timer_init(struct device_node *np) * 4) Channel0 disabled * 5) DMA transfers disabled */ + /* make sure counter is disabled */ writel(0, timer_base + TPM_SC); + /* TOF is W1C */ + writel(TPM_SC_TOF_MASK, timer_base + TPM_SC); writel(0, timer_base + TPM_CNT); - writel(0, timer_base + TPM_C0SC); + /* CHF is W1C */ + writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC); /* increase per cnt, div 8 by default */ writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,