From patchwork Wed Mar 14 18:15:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 131704 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp154386ljb; Wed, 14 Mar 2018 11:19:52 -0700 (PDT) X-Google-Smtp-Source: AG47ELu+2PnL4zlnq9Sv2InH8dxjEHBcfORN7ke0OHFzc1sxD/Yc/m0s7iR7gdAOmboipEVQeZwM X-Received: by 2002:a17:902:858c:: with SMTP id e12-v6mr5013108plo.39.1521051592323; Wed, 14 Mar 2018 11:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521051592; cv=none; d=google.com; s=arc-20160816; b=FMqbyo2CWeePO9+od6o6ls3vg9EkgQPA+QPpJtwRPUOGkrFz10qvpnnU3A1IBvWpT7 0PxuvzpDaLqouou5zbOCdxrMAql8AuLNCpi1ksBAzciiuO54OLH6u9RYWKu0CRClHcB/ 2eKxWEwZia7B4IBtsrviAjXvU5dODYAvrbfbis03+ZngT4Omcy0BUq4EEFOnKfcq3+gu Ib1OyfDEnmAPuVQNWrUuxlZ4piG3H4jdDe/g+ZvOf9N+C5j1zFZwwJrBWpfRGwGCEC/n +J/S4wxEjFjh91AeY+gtc1Au7asNDkbdWtD42vkiXVt1iz8Z1i84wW5kGRCwocoXnJjl gN5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=YY5/xfa6Q6jO3B9AmF91X3fG8bvtn1Lz1KUNcgUPL3E=; b=dWVIY2n9ceLLuhrU2TKnShTE6IwbSIj/bC0b3vi1SHIbagmdVutmYL18T6uBouOssK 2nUk6PZFJaXmKnf6amngDCn/OBOFZeQ02v/rUfNYC4R+y2YkcBY0a2GnQsNi4vcxpDhI quwDo9djM02LDfg/SVLk9TReyRtJP2Ma4Y580kfQYJeuqU8Yj0ptMeNljnwqMTzBrtbj qQZ1vqTA2FBTc/kNVZv2e0jKCcTQ0wmQ9cTpr4Hkkc149neYOE/NMFbxKN2cDQbSwrzT mpBHp7ziPsP+Y1eFKDDy/bDIJNcO9nMsMsMZ/oemIruEQdY9HvYEXlwCwFlykSoICme4 jaLg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 197si2247117pge.78.2018.03.14.11.19.52; Wed, 14 Mar 2018 11:19:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751982AbeCNSRI (ORCPT + 28 others); Wed, 14 Mar 2018 14:17:08 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6201 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750862AbeCNSRF (ORCPT ); Wed, 14 Mar 2018 14:17:05 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 1652E17F2F6E1; Thu, 15 Mar 2018 02:16:51 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.361.1; Thu, 15 Mar 2018 02:16:45 +0800 From: John Garry To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v17 04/10] PCI: Apply the new generic I/O management on PCI IO hosts Date: Thu, 15 Mar 2018 02:15:53 +0800 Message-ID: <1521051359-34473-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521051359-34473-1-git-send-email-john.garry@huawei.com> References: <1521051359-34473-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan After introducing the new generic I/O space management(Logical PIO), the original PCI MMIO relevant helpers need to be updated based on the new interfaces defined in logical PIO. This patch adapts the corresponding code to match the changes introduced by logical PIO. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Tested-by: dann frazier --- drivers/pci/pci.c | 92 +++++++++--------------------------------------- include/asm-generic/io.h | 2 +- 2 files changed, 18 insertions(+), 76 deletions(-) -- 1.9.1 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 3f30b7d..09c2490 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -3436,17 +3437,6 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) } EXPORT_SYMBOL(pci_request_regions_exclusive); -#ifdef PCI_IOBASE -struct io_range { - struct list_head list; - phys_addr_t start; - resource_size_t size; -}; - -static LIST_HEAD(io_range_list); -static DEFINE_SPINLOCK(io_range_lock); -#endif - /* * Record the PCI IO range (expressed as CPU physical address + size). * Return a negative value if an error has occured, zero otherwise @@ -3454,51 +3444,28 @@ struct io_range { int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, resource_size_t size) { - int err = 0; - + int ret = 0; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - /* check if the range hasn't been previously recorded */ - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (addr >= range->start && addr + size <= range->start + size) { - /* range already registered, bail out */ - goto end_register; - } - allocated_size += range->size; - } + struct logic_pio_hwaddr *range; - /* range not registed yet, check for available space */ - if (allocated_size + size - 1 > IO_SPACE_LIMIT) { - /* if it's too big check if 64K space can be reserved */ - if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { - err = -E2BIG; - goto end_register; - } - - size = SZ_64K; - pr_warn("Requested IO range too big, new size set to 64K\n"); - } + if (!size || addr + size < addr) + return -EINVAL; - /* add the range to the list */ range = kzalloc(sizeof(*range), GFP_ATOMIC); - if (!range) { - err = -ENOMEM; - goto end_register; - } + if (!range) + return -ENOMEM; - range->start = addr; + range->fwnode = fwnode; range->size = size; + range->hw_start = addr; + range->flags = LOGIC_PIO_CPU_MMIO; - list_add_tail(&range->list, &io_range_list); - -end_register: - spin_unlock(&io_range_lock); + ret = logic_pio_register_range(range); + if (ret) + kfree(range); #endif - return err; + return ret; } phys_addr_t pci_pio_to_address(unsigned long pio) @@ -3506,21 +3473,10 @@ phys_addr_t pci_pio_to_address(unsigned long pio) phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - if (pio > IO_SPACE_LIMIT) + if (pio >= MMIO_UPPER_LIMIT) return address; - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (pio >= allocated_size && pio < allocated_size + range->size) { - address = range->start + pio - allocated_size; - break; - } - allocated_size += range->size; - } - spin_unlock(&io_range_lock); + address = logic_pio_to_hwaddr(pio); #endif return address; @@ -3529,21 +3485,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio) unsigned long __weak pci_address_to_pio(phys_addr_t address) { #ifdef PCI_IOBASE - struct io_range *res; - resource_size_t offset = 0; - unsigned long addr = -1; - - spin_lock(&io_range_lock); - list_for_each_entry(res, &io_range_list, list) { - if (address >= res->start && address < res->start + res->size) { - addr = address - res->start + offset; - break; - } - offset += res->size; - } - spin_unlock(&io_range_lock); - - return addr; + return logic_pio_trans_cpuaddr(address); #else if (address > IO_SPACE_LIMIT) return (unsigned long)-1; diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index f76fbd6..0016413 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -901,7 +901,7 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) #define ioport_map ioport_map static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { - return PCI_IOBASE + (port & IO_SPACE_LIMIT); + return PCI_IOBASE + (port & MMIO_UPPER_LIMIT); } #endif