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[209.132.180.67]) by mx.google.com with ESMTP id l11-v6si689864pln.323.2018.02.27.20.55.47; Tue, 27 Feb 2018 20:55:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TWvhRrb4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751973AbeB1Ezn (ORCPT + 28 others); Tue, 27 Feb 2018 23:55:43 -0500 Received: from mail-qk0-f196.google.com ([209.85.220.196]:39093 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751679AbeB1Ezk (ORCPT ); Tue, 27 Feb 2018 23:55:40 -0500 Received: by mail-qk0-f196.google.com with SMTP id z197so1498512qkb.6 for ; Tue, 27 Feb 2018 20:55:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=TWvhRrb4nOj2fylSyrnJpUm55JQR7TCW+gHkz2VXCND8UD2YX+lsaB6QJv+O/xd/zE 62MnNN0xt3vpH2WzONkzdxpL7aS9I9WwiaecygWrKTiOKtDFihnhVb7mwEhIWufBwkcm 3XEpJEJvUiKQ9dsCWt7JyBFKuihwpeP0q22ho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=oTb0WGt8ra/YSYxfAnvPrjWIpDwxFxik6vCIvbIsDu/fNraIb7wbFuvFwL91N6YRyj rLyXfLG7Kn06Grmr2EbjWs8fvEJt+Nj3osNw05JVJWDCzztuHHvNwUMXyZGp8ZVjXi1C ioNThQCTR2OvSGIoLrCKEEUCKreU1Lk7IaYJBXt110y8Z7yfXNMggHWVm41IjGnMZf+2 qXhPYuPkhul0IEhqW1cZH3mB82ovtl5LJ/1xeJhLgsTpcVX06nZCRcdrcA2yjqgHI7lZ /mljLcyIfFB0Fae7F9sUKBrGr8pFMh6dB5sVXqzgCf6YwoAQMMpgv+m73wBJOaL5Goav smMw== X-Gm-Message-State: APf1xPBYh2OZ7vUoAOgdJdnbwPd/zZpg5zxtyY7Y0mW4X1fRcA5h5KN3 sLQEg1+elTC9mzvdamDAeTnFGA== X-Received: by 10.55.221.198 with SMTP id u67mr26987603qku.91.1519793739377; Tue, 27 Feb 2018 20:55:39 -0800 (PST) Received: from localhost.localdomain ([45.77.212.61]) by smtp.gmail.com with ESMTPSA id 2sm596728qkv.2.2018.02.27.20.55.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 20:55:38 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Jassi Brar , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kaihua Zhong , Guodong Xu , Haojian Zhuang Cc: Leo Yan Subject: [PATCH v6 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding Date: Wed, 28 Feb 2018 12:54:53 +0800 Message-Id: <1519793695-20198-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> References: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt new file mode 100644 index 0000000..3e5b453 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt @@ -0,0 +1,51 @@ +Hisilicon Hi3660 Mailbox Controller + +Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages +are passed between processors, including application & communication +processors, MCU, HIFI, etc. Each channel is unidirectional and accessed +by using MMIO registers; it supports maximum to 8 words message. + +Controller +---------- + +Required properties: +- compatible: : Shall be "hisilicon,hi3660-mbox" +- reg: : Offset and length of the device's register set +- #mbox-cells: : Must be 3 + <&phandle channel dst_irq ack_irq> + phandle : Label name of controller + channel : Channel number + dst_irq : Remote interrupt vector + ack_irq : Local interrupt vector + +- interrupts: : Contains the two IRQ lines for mailbox. + +Example: + +mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = <0x0 0xc0 0x4>, + <0x0 0xc1 0x4>; + #mbox-cells = <3>; +}; + +Client +------ + +Required properties: +- compatible : See the client docs +- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) + Cells must match 'mbox-cells' (See Controller docs above) + +Optional properties +- mbox-names : Name given to channels seen in the 'mboxes' property. + +Example: + +stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; +};