From patchwork Wed Feb 28 03:56:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129887 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp567526lja; Tue, 27 Feb 2018 19:57:57 -0800 (PST) X-Google-Smtp-Source: AG47ELtLGWYp4YespeEvuPr5XhxIIlM2YOdJ/ItcRPW39wH/A2ZC1MHdEWDloGkQfeX7yMaFSGIs X-Received: by 2002:a17:902:1c5:: with SMTP id b63-v6mr10136385plb.311.1519790277799; Tue, 27 Feb 2018 19:57:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519790277; cv=none; d=google.com; s=arc-20160816; b=fSvlX7QH9uyXIesl0VI7M0/GbjAtrIMcBjQ2KXeyR70XiMLFyncs83Rj7RyxdAc56z 11f4oJDxUBYTbABOXx3v1QNJeW005pq3xm9aYl/7jgl3BYsJ+GBB9T/RJwxj+ynP68P+ D7ZoObsMAKWKSHwecHD/7Jss5joJzTR1ZKDxL3aF99ydpvytSQCKrbLDjVxX5QSfZo5G g6Bn688tzzdMlLvcNtPcT7FkKY6NpJXQY39HqOaRLuvoSX7B5xkEpKS6OkL4IKz7UG/z dVo624x7p3SYUm4k6bpGJIx9cfvkE49Avmu9Swwz4yO20WPgTh1hdLrwpo3ZgTcW3NcW lhJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ei8K/u/Kw0usIbJStlCx/X9r89lOl79D4a+wZXmBbiM=; b=Vr0DPPVdBuxo31DlsfXQ//YlIqDC6VZ4FCEm4lXMDV7C2xDCJpnCv8ZHYzfp5wvSla xQbeQ1/2Tft15U7y+zUZVo3MYjZYOH0r5mlh5IuY0clT5FGOISzu462eGp1IyYyl07s+ dcM6gQqEOKU13x39dGhlVog4rrV2FRCDVJOapwdqOdjCYyhWxbGnsVCURNRYX3MWE39V 6Okpg3a+rVHVCc4kXEoBHdeKoDSxdBhigLmQF+sZoh58KuqJGLhqrBSjcHC/uq6T+Vfu B26U7Z2uszgMUhOAhndQPEjKW+7Ip6v4J66Wvr/woWzqkXlIGz8wbGJLDuHWHngO/JJN 5RlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CZzvQxfG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l7-v6si585896pls.331.2018.02.27.19.57.57; Tue, 27 Feb 2018 19:57:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CZzvQxfG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751974AbeB1D5y (ORCPT + 28 others); Tue, 27 Feb 2018 22:57:54 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:33262 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751942AbeB1D5v (ORCPT ); Tue, 27 Feb 2018 22:57:51 -0500 Received: by mail-pg0-f67.google.com with SMTP id g12so488888pgs.0 for ; Tue, 27 Feb 2018 19:57:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ei8K/u/Kw0usIbJStlCx/X9r89lOl79D4a+wZXmBbiM=; b=CZzvQxfGCOfcVKhg6pOWxmK47Ud0F1tSf+xrA5i8+vKVVK/iB8PxIybac2G9IC3+/H s5Twa2tpfLCaY5kOJezW1ZenNaxqMW772gswWBWGf0B7ICIetliL4yPe/lfH7nbMR+JP YK6gVh2+8kyh/Ds57Us4sh6KDtkpTvDAQunmw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ei8K/u/Kw0usIbJStlCx/X9r89lOl79D4a+wZXmBbiM=; b=FxksF6Xd/xesEODLmFKIDfvZGp/yToDnclpllIv9GZWZ8wdDxIZcYgUh8iPIwDYj09 GN6FuOgiZ7+CXz88cZsI1PoX1xiGbMPIGIwFYoRKGtzWow3wJnz4XfjKFP0jIRFV/842 OxysxDYdn/27bAZH9IRgH8Wt43gs7gyk89kPXLLXq6Bjk1qONIqjlioSqnK/v5++6qEh 310EFV051yTZ7BN32A1gJ0UakJ0UXCM24//nJjbaCbafkApzy8SZ9L3MqqQ7ur+HAuYV REssWAN3W58eY+xF84+JY1g/8KGiaf1RvwRTHUl8e+Yabq1QBuNK+LNAcCm/TO84tjY2 EQiQ== X-Gm-Message-State: APf1xPD0hzpx0JGTz5YmOhcOrdRL6pDddNXuLMO/rEn7YIaj3grTy4Kw 3WRnLS4XNs7SYlQiqJ5e7xBiDQ== X-Received: by 10.101.81.204 with SMTP id i12mr13054782pgq.206.1519790270814; Tue, 27 Feb 2018 19:57:50 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id q17sm739911pgt.7.2018.02.27.19.57.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 19:57:50 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alex Shi Subject: [PATCH 03/29] arm64: mm: Allocate ASIDs in pairs Date: Wed, 28 Feb 2018 11:56:25 +0800 Message-Id: <1519790211-16582-4-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> References: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon commit 0c8ea531b774 upstream. In preparation for separate kernel/user ASIDs, allocate them in pairs for each mm_struct. The bottom bit distinguishes the two: if it is set, then the ASID will map only userspace. Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by: Shanker Donthineni Signed-off-by: Will Deacon Signed-off-by: Alex Shi Conflicts: no MMCF_AARCH32 in arch/arm64/include/asm/mmu.h --- arch/arm64/include/asm/mmu.h | 2 ++ arch/arm64/mm/context.c | 25 +++++++++++++++++-------- 2 files changed, 19 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 8d9fce0..49924e5 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,6 +16,8 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#define USER_ASID_FLAG (UL(1) << 48) + typedef struct { atomic64_t id; void *vdso; diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index efcf1f7..f00f5ee 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -39,7 +39,16 @@ static cpumask_t tlb_flush_pending; #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) #define ASID_FIRST_VERSION (1UL << asid_bits) -#define NUM_USER_ASIDS ASID_FIRST_VERSION + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +#define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1) +#define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1) +#define idx2asid(idx) (((idx) << 1) & ~ASID_MASK) +#else +#define NUM_USER_ASIDS (ASID_FIRST_VERSION) +#define asid2idx(asid) ((asid) & ~ASID_MASK) +#define idx2asid(idx) asid2idx(idx) +#endif /* Get the ASIDBits supported by the current CPU */ static u32 get_cpu_asid_bits(void) @@ -104,7 +113,7 @@ static void flush_context(unsigned int cpu) */ if (asid == 0) asid = per_cpu(reserved_asids, i); - __set_bit(asid & ~ASID_MASK, asid_map); + __set_bit(asid2idx(asid), asid_map); per_cpu(reserved_asids, i) = asid; } @@ -159,16 +168,16 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) * We had a valid ASID in a previous life, so try to re-use * it if possible. */ - asid &= ~ASID_MASK; - if (!__test_and_set_bit(asid, asid_map)) + if (!__test_and_set_bit(asid2idx(asid), asid_map)) return newasid; } /* * Allocate a free ASID. If we can't find one, take a note of the - * currently active ASIDs and mark the TLBs as requiring flushes. - * We always count from ASID #1, as we use ASID #0 when setting a - * reserved TTBR0 for the init_mm. + * currently active ASIDs and mark the TLBs as requiring flushes. We + * always count from ASID #2 (index 1), as we use ASID #0 when setting + * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd + * pairs. */ asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); if (asid != NUM_USER_ASIDS) @@ -185,7 +194,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) set_asid: __set_bit(asid, asid_map); cur_idx = asid; - return asid | generation; + return idx2asid(asid) | generation; } void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)