From patchwork Wed Feb 28 03:56:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129907 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp569238lja; Tue, 27 Feb 2018 20:00:25 -0800 (PST) X-Google-Smtp-Source: AH8x224grW61XOSGypq1Izmny+qK3oF7sS6XzIuMf8I0gZiq7tvefc7xGmx6eurQ1ERWazokkI9e X-Received: by 10.99.113.94 with SMTP id b30mr13103480pgn.228.1519790425741; Tue, 27 Feb 2018 20:00:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519790425; cv=none; d=google.com; s=arc-20160816; b=NUypNSBeEa7lysYKVdiPpHQVdWXFCm6Qgp13414aWINfg5Vy8UewVmfYUWnvF2Sh0Z zd1O4eqN0PPwDlR+ikQUvQB2dBhHR9ty2+JCcPVb1IzTvyeLTv3AaDM6/72rtsQCx5Cw V8/Eb5Xw8eZ/4pUp6E33GLsmBSkxaPddyc3hNMyL4IdsT9yP/b0LupK2TffLl54x2tp2 NMBI/9ONJdz6CzyrKpKd3UyGZR5OpdFNLCCeu1xXcnKeH0m6WdD48ZUpa9UqOp85h8Xl kiLd2s+XVPnrGrfnWoZxL0t7N2KONcljK+khEmuOG2YKWSjXt7H0sqIBFmAhAC1lERnM wG8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=PoybqqZSHPpCwyXKEdU/iRxK/k+IGVxzQYoov7ys+2E=; b=Vgjrvo4pX7UMbG+mXp4tL7nFoiJTi0KF5VoDsfJUK938+6hdrssLOgoE9NUm6bL1WZ uCPKmGOnOJYAi0DRn1YHCc8uRcv4x+7hWE1sGxmtGWeqYax1WIt6HQjxfRQTh2RWkhwv miHpP9YYce4WHeaCtXdyliQUMbkJPMdzlKZVaM+haPBWx4xBenGd0dxQ9/xy2VZvfSUi te1OMkFLYH3l3Q7z+h6ydMOco39JWc2FE3zYtbuKLQisDQ3WErA0etOEw1ZWn8hS/BYk olbWE+/8SAgZRWg86VDwotNJqaR9gwEO61Bz1hpr1cw1XgAe1fFCHJZSPFd4MtVb90Vp ggTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V2xzAr5l; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g17-v6si571790plo.357.2018.02.27.20.00.25; Tue, 27 Feb 2018 20:00:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V2xzAr5l; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752333AbeB1EAW (ORCPT + 28 others); Tue, 27 Feb 2018 23:00:22 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:33054 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752016AbeB1EAT (ORCPT ); Tue, 27 Feb 2018 23:00:19 -0500 Received: by mail-pl0-f68.google.com with SMTP id c11-v6so781780plo.0 for ; Tue, 27 Feb 2018 20:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PoybqqZSHPpCwyXKEdU/iRxK/k+IGVxzQYoov7ys+2E=; b=V2xzAr5ltQF3Hy5DzYI7m0s+Jq/7VIZsaznsw8u2ieV7wLDRS3JWdiR3zv5GOsnlxK v7AKjNgPvqlnp9pS4AEG+Os6QXOAm1k8qztqzfYmwlywHqlzmCPZ8Ly2U6wTULhAenUM UocwCi2bPX1pVi5fAC/66MX27GrzfEaggT7EA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PoybqqZSHPpCwyXKEdU/iRxK/k+IGVxzQYoov7ys+2E=; b=tBRhWXIyUv51cLim6l+Hb0XkVeKrKeGZdzAnge7tANOU1XErijKcJDePCq2rWdJvqm dIcfBfMazhGWLelPUJG7dgAVKZHrzbJAjtStKp3optEBooI8iri4ASsSzOpUZF8tBrT2 j7o6qCWECkM/wf4z1g4m0jNyBc9rnFib9ONfmoEhveXRVeQ6Ydm3OeK4SDD3dxNdsydi vwEB5tayZVbgoUuOaNXjGzRkJ5tA4GSocbzhVkpiDKg9vxq4d24JOCU6caE6QOHzdl93 yQ11yyAKol0RZZ32i2S7oFXmMizkuW+FDySKDMlGEbilISl8Ns0rUJj8jVJoEVJ6a4uT E/yA== X-Gm-Message-State: APf1xPAlb1mYJDwDUgy1bdVOxIrLYhF9x9hKKfgoB+q00WnLRhL0pTJ5 qSI7Osn+0ljIt95lw1gNkZYA9g== X-Received: by 2002:a17:902:7404:: with SMTP id g4-v6mr16390270pll.235.1519790419043; Tue, 27 Feb 2018 20:00:19 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id q17sm739911pgt.7.2018.02.27.20.00.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 20:00:18 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Jayachandran C , Alex Shi Subject: [PATCH 23/29] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Wed, 28 Feb 2018 11:56:45 +0800 Message-Id: <1519790211-16582-24-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> References: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jayachandran C commit 0d90718871fe upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Alex Shi Conflicts: no falkor support in arch/arm64/include/asm/cputype.h --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 0843b3f..9ee3038 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -84,6 +84,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -94,6 +95,8 @@ #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #ifndef __ASSEMBLY__