From patchwork Mon Feb 26 16:40:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129693 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp3975414edc; Mon, 26 Feb 2018 07:52:03 -0800 (PST) X-Google-Smtp-Source: AH8x225VT/OTpPauboa5G1j8PM+GuGrTt7zu9aRg7oVTSt7Xfmdujjxi1Xf8E0wu6xt1yIC3gW+Q X-Received: by 10.98.19.146 with SMTP id 18mr11069746pft.3.1519660323548; Mon, 26 Feb 2018 07:52:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519660323; cv=none; d=google.com; s=arc-20160816; b=QA0CY/dzMdCovi4g/zM5GrGI2HVLO7hrWC6OUqBNwhYwAlvAhXrp/vEWY1LVUeMU9z KO47zU1i6q6mG+ftYfD9Yq7TPQVcN+do6v8w86BAUssJzNe5FAPm+5BMA69R3Wx3MO3n Vi8Tw8vVr6mj2S3OOKb11pemfEJEqnnZTrDQJ1BEppDyK35kqyXN7S/izaa9CSSsuElP m0vl6h/PEEbINGXBxKAMUOdpjFd3R0F2Ra1rYxdQO7UXM4OepUHubHL8viuJL7/Fk5vH 9tB6lUAD8XOKfjki4HND/tsr4UgqKlC6SpxpAa0aRNcpqV4N2y7EbD6EnOJ9n0AX42Ts lN1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=yHujM6xcjQYoK4GeKKJ+aO72txxyen4/fJ8zNv0jvus=; b=aVnHO61GQ5hEYiiyilCSiw9+TA5TVr/DdCIevYEDt1bsiXs/vlM69hsBvN8KgXkaqJ A1lwuzz/NT4eK+UmW5vh5bz8xwzjDz8yX/W5o7/TiVsyoXykp+9y3rdBHw0sbxMHprvv OM232MfgN5qPPYQ4BH0f7AYaun0V3lD8LPxNl/n7wMQq1X41bjrjIFFBL2jvdDZHLl5M INQ0eUcfRlmuONCWkNNu259CPf19mCi+r5S0fruiMO8marO6w2FDN0Xdu1/PRe+tSRPm dP9gr2SMMUkdUNxcESV7f3GSNaZmGj75/9MWWaZuEitHl7Buq0UWH7HaHx2XOxZwuqs/ aALw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e123si5670872pgc.406.2018.02.26.07.52.03; Mon, 26 Feb 2018 07:52:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752431AbeBZPwA (ORCPT + 28 others); Mon, 26 Feb 2018 10:52:00 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:49344 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751671AbeBZPuV (ORCPT ); Mon, 26 Feb 2018 10:50:21 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 0FFF733B75693; Mon, 26 Feb 2018 23:50:06 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Mon, 26 Feb 2018 23:49:59 +0800 From: John Garry To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v15 4/9] PCI: Apply the new generic I/O management on PCI IO hosts Date: Tue, 27 Feb 2018 00:40:44 +0800 Message-ID: <1519663249-9850-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519663249-9850-1-git-send-email-john.garry@huawei.com> References: <1519663249-9850-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan After introducing the new generic I/O space management(Logical PIO), the original PCI MMIO relevant helpers need to be updated based on the new interfaces defined in logical PIO. This patch adapts the corresponding code to match the changes introduced by logical PIO. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Tested-by: dann frazier --- drivers/pci/pci.c | 92 +++++++++--------------------------------------- include/asm-generic/io.h | 2 +- 2 files changed, 18 insertions(+), 76 deletions(-) -- 1.9.1 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 07290a3..83a263f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -3440,17 +3441,6 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) } EXPORT_SYMBOL(pci_request_regions_exclusive); -#ifdef PCI_IOBASE -struct io_range { - struct list_head list; - phys_addr_t start; - resource_size_t size; -}; - -static LIST_HEAD(io_range_list); -static DEFINE_SPINLOCK(io_range_lock); -#endif - /* * Record the PCI IO range (expressed as CPU physical address + size). * Return a negative value if an error has occured, zero otherwise @@ -3458,51 +3448,28 @@ struct io_range { int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, resource_size_t size) { - int err = 0; - + int ret = 0; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - /* check if the range hasn't been previously recorded */ - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (addr >= range->start && addr + size <= range->start + size) { - /* range already registered, bail out */ - goto end_register; - } - allocated_size += range->size; - } + struct logic_pio_hwaddr *range; - /* range not registed yet, check for available space */ - if (allocated_size + size - 1 > IO_SPACE_LIMIT) { - /* if it's too big check if 64K space can be reserved */ - if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { - err = -E2BIG; - goto end_register; - } - - size = SZ_64K; - pr_warn("Requested IO range too big, new size set to 64K\n"); - } + if (!size || addr + size < addr) + return -EINVAL; - /* add the range to the list */ range = kzalloc(sizeof(*range), GFP_ATOMIC); - if (!range) { - err = -ENOMEM; - goto end_register; - } + if (!range) + return -ENOMEM; - range->start = addr; + range->fwnode = fwnode; range->size = size; + range->hw_start = addr; + range->flags = LOGIC_PIO_CPU_MMIO; - list_add_tail(&range->list, &io_range_list); - -end_register: - spin_unlock(&io_range_lock); + ret = logic_pio_register_range(range); + if (ret) + kfree(range); #endif - return err; + return ret; } phys_addr_t pci_pio_to_address(unsigned long pio) @@ -3510,21 +3477,10 @@ phys_addr_t pci_pio_to_address(unsigned long pio) phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - if (pio > IO_SPACE_LIMIT) + if (pio >= MMIO_UPPER_LIMIT) return address; - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (pio >= allocated_size && pio < allocated_size + range->size) { - address = range->start + pio - allocated_size; - break; - } - allocated_size += range->size; - } - spin_unlock(&io_range_lock); + address = logic_pio_to_hwaddr(pio); #endif return address; @@ -3533,21 +3489,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio) unsigned long __weak pci_address_to_pio(phys_addr_t address) { #ifdef PCI_IOBASE - struct io_range *res; - resource_size_t offset = 0; - unsigned long addr = -1; - - spin_lock(&io_range_lock); - list_for_each_entry(res, &io_range_list, list) { - if (address >= res->start && address < res->start + res->size) { - addr = address - res->start + offset; - break; - } - offset += res->size; - } - spin_unlock(&io_range_lock); - - return addr; + return logic_pio_trans_cpuaddr(address); #else if (address > IO_SPACE_LIMIT) return (unsigned long)-1; diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index f76fbd6..0016413 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -901,7 +901,7 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) #define ioport_map ioport_map static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { - return PCI_IOBASE + (port & IO_SPACE_LIMIT); + return PCI_IOBASE + (port & MMIO_UPPER_LIMIT); } #endif