From patchwork Mon Feb 26 08:20:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129596 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3359465lja; Mon, 26 Feb 2018 00:27:17 -0800 (PST) X-Google-Smtp-Source: AH8x227NKza38lIoxLamJP2kXSxeVlXXz6EN/SNNbYiF93S9UBHGnvCk7QdsipHEDcgyMrHzRiYR X-Received: by 2002:a17:902:8f97:: with SMTP id z23-v6mr9928329plo.162.1519633637755; Mon, 26 Feb 2018 00:27:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519633637; cv=none; d=google.com; s=arc-20160816; b=VkFFnKC6OG+8Nt1T38ahI7pk16PKFE60OhOsJVn6gtYSTGmX4kleQgG1igGQ6a81zB VSrTJs9c7FKa6EYzi/0lYjdMvZNWQC0hiEOd8C0WAK2Xtw/nMXuQVgeYYBe17kjHZ8Cu Fkpd5Q84FSqTgPkw0Lu4vk9o2IAsE2jbE5kb9KlvHVjl3nIwgC5s9MdnjEJxYUdx7bxP 3J/MsJ9ZVu5Ki4+W5stXbgf6V+A6rLW0hY2e8fvkBeLgTfABrdE8L9U9JJedFU4f4dBX xOBVroz6mqyKFE1gKa7HlqMybjy+xWuOzJSx8fQAJdVPnbl4oBR30Dep+RzleIInhf6o cI3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=FrYQc7jNWo3H77WRAN83meLx1vfqAFkomM5c8aD6cAQ=; b=APAy9XqCKqq/RJ0BYfl+OTQ7p4mEnuleEsqT0zycFm3uxqRjHsFdEE6yzaMfcndy/+ 4hk5Tya1B+uu1O/Ag3wPHakl9sGp+hEpkPSfWyb6AUzDYCq52ZRDs9UqPsDNW9wJeh/m 1cZjwHJ+ktVeAze3re50xtEHju1BIZy/rtjupfpunOq3EnxS94SDa6yCWyzXSlmZOAje LadxvObPr1FZ5bpqRVnPGqQmtAGLmHP0O1YGqunOR8kCQlIzMB0COufspheiCATVDVkf y5xkMlxKu8ZskZCzsg/JuBHKyGX7hTO+jdeYKLiPuuO6xBfFz0Z4qJkKbkPBGK2L03Lw IIzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PMncHEnw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s190si5281566pgc.510.2018.02.26.00.27.17; Mon, 26 Feb 2018 00:27:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PMncHEnw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752840AbeBZI1O (ORCPT + 28 others); Mon, 26 Feb 2018 03:27:14 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:40189 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752804AbeBZI1B (ORCPT ); Mon, 26 Feb 2018 03:27:01 -0500 Received: by mail-pf0-f196.google.com with SMTP id m5so6219285pff.7 for ; Mon, 26 Feb 2018 00:27:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=FrYQc7jNWo3H77WRAN83meLx1vfqAFkomM5c8aD6cAQ=; b=PMncHEnwzW+oNl0sJH7ZLS5EK4JoEBtJGeg9w9/zhui1CandURqm0suWxeiXDh7FLc lKIIJsDxvJqVKtIGyda3nQd5HYUOJ6XeKO0cbNDuJrXp9QauHuFpj7/JoNetQGK3dilp lvcIAy+4IJJsnKUAWBuhoygJ+eMujemLUAjNg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=FrYQc7jNWo3H77WRAN83meLx1vfqAFkomM5c8aD6cAQ=; b=OII0QXXSmfkVZMAoBuFgDDpeoGewQVwm8kH+mCYX8gCncGy56EJiWNFKVLMDBUcuKy FwWEPiLiNO7nGAYFwLaRZOKwbufiI6XJ6UGOO7xPvrkCTETfZhEn9xQqvdzjhrgHKoAd /op+9wNg0Isv5kTpxc/JI5eczwa4728NXlBzx/m5rn5qL4IwP2gY5gAUFoLNCAKyGYDK HpbMj5+2KAvfVMDu6aN/0b0qqyqyuFzvleaCIi+vMdT8BbGy0I16wb5JZyIsHu1u+jQs ei+ZeZPVNzqAzo6PvdAnNeqrhvHauo+ezZDrM2cmbJI7qPY8fLQP98+NSZ2bXydP5Udq vRXA== X-Gm-Message-State: APf1xPB1C4YAoLvr0eLza5pC9cd/rRWsBGmy4GmyEnhNqGttCavV5afF 19n+2A4V5n2/Y5aVTadiTA5fQg== X-Received: by 10.98.28.202 with SMTP id c193mr9816366pfc.109.1519633620617; Mon, 26 Feb 2018 00:27:00 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id o86sm1422706pfi.87.2018.02.26.00.26.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 00:27:00 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, Christoffer Dall , Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list), kvmarm@lists.cs.columbia.edu (open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)), kvm@vger.kernel.org (open list:KERNEL VIRTUAL MACHINE (KVM)) Subject: [PATCH 45/52] arm64: Kill PSCI_GET_VERSION as a variant-2 workaround Date: Mon, 26 Feb 2018 16:20:19 +0800 Message-Id: <1519633227-29832-46-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> References: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier commit 3a0a397ff5ff upstream. Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Alex Shi Conflicts: no falkor/thunderx2/vulcan in arch/arm64/kernel/cpu_errata.c --- arch/arm64/kernel/bpi.S | 24 ------------------------ arch/arm64/kernel/cpu_errata.c | 41 +++++++++++------------------------------ arch/arm64/kvm/hyp/switch.c | 14 -------------- 3 files changed, 11 insertions(+), 68 deletions(-) -- 2.7.4 diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index c72f261..dc4eb15 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -54,30 +54,6 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) .macro smccc_workaround_1 inst sub sp, sp, #(8 * 4) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 9632319..8b74f80 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -53,7 +53,6 @@ static int cpu_enable_trap_ctr_access(void *__unused) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; extern char __smccc_workaround_1_hvc_start[]; @@ -100,8 +99,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else -#define __psci_hyp_bp_inval_start NULL -#define __psci_hyp_bp_inval_end NULL #define __smccc_workaround_1_smc_start NULL #define __smccc_workaround_1_smc_end NULL #define __smccc_workaround_1_hvc_start NULL @@ -146,24 +143,25 @@ static void call_hvc_arch_workaround_1(void) arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); } -static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { + const struct arm64_cpu_capabilities *entry = data; bp_hardening_cb_t cb; void *smccc_start, *smccc_end; struct arm_smccc_res res; if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return false; + return 0; if (psci_ops.smccc_version == SMCCC_VERSION_1_0) - return false; + return 0; switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_hvc_arch_workaround_1; smccc_start = __smccc_workaround_1_hvc_start; smccc_end = __smccc_workaround_1_hvc_end; @@ -173,35 +171,18 @@ static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *e arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_smc_arch_workaround_1; smccc_start = __smccc_workaround_1_smc_start; smccc_end = __smccc_workaround_1_smc_end; break; default: - return false; + return 0; } install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); - return true; -} - -static int enable_psci_bp_hardening(void *data) -{ - const struct arm64_cpu_capabilities *entry = data; - - if (psci_ops.get_version) { - if (check_smccc_arch_workaround_1(entry)) - return 0; - - install_bp_hardening_cb(entry, - (bp_hardening_cb_t)psci_ops.get_version, - __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); - } - return 0; } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -301,22 +282,22 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif { diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 996328e..154b471 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -311,20 +311,6 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu)) goto again; - if (exit_code == ARM_EXCEPTION_TRAP && - (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC64 || - kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC32)) { - u32 val = vcpu_get_reg(vcpu, 0); - - if (val == PSCI_0_2_FN_PSCI_VERSION) { - val = kvm_psci_version(vcpu, kern_hyp_va(vcpu->kvm)); - if (unlikely(val == KVM_ARM_PSCI_0_1)) - val = PSCI_RET_NOT_SUPPORTED; - vcpu_set_reg(vcpu, 0, val); - goto again; - } - } - if (static_branch_unlikely(&vgic_v2_cpuif_trap) && exit_code == ARM_EXCEPTION_TRAP) { bool valid;