From patchwork Mon Feb 26 08:19:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129559 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3355584lja; Mon, 26 Feb 2018 00:21:36 -0800 (PST) X-Google-Smtp-Source: AH8x2277yj/4RDhanBZ+LyHtB43LK6OqQwb+4tGED4aula1vZjcJkhwu2ltxITIZ1xHM6oZ92kVe X-Received: by 2002:a17:902:a985:: with SMTP id bh5-v6mr9735264plb.230.1519633296105; Mon, 26 Feb 2018 00:21:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519633296; cv=none; d=google.com; s=arc-20160816; b=Shk8EUySImMrnZOtzTTmFO1y32BzBfUHTP829ypzWW2FUTGaKGKoafr9/y5JU2JA+K lWRDpSIFxcFG/gs50j8V+fYgTohrOHlYtLnE40KWUYMQUxatR1DeUsho5Iz7Nvn0rkRp v+Io58nXmNmKVEeGRYGgjHhNxjmQ+lI3gHizVMWliwX87ppxBSxRpBN5vZ16BegIgemG hbv8tBgJPe2cfB/gQu/7cXZBrmq3VIJDcOxT1A01lywuMB/j0D5s4D7cd+8ZaCUVtr3O kERM/fjuJUtG7MjoRYrjPVGZiSouPrx6apx2vS16jb3ZyjZNZB5aY9WeV2dT5XXF3fPI 2jKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=5jc9doNqehmWExc3XoeNI1qQ6N7FZfbJliUkP3bf70M=; b=rky8RP6iZf9UlOmt6IEbB4fCDBI9XpoHODCzA0+Y8Np//G9W4j77gpjYCDMvODpDSr ANCAI0kIICRQ8R/4w0hJE3R9bpn9vl9Vzm6wcsn06x6TkF2cS3iqRaZhihDLyhrxKxKA wpa5mS2quak+eKXIWZEeqExMMi16k8J/zQE3s8Zqz33d2ahmFmn5NrrV+9DDXv19PDO/ G2+zdx0TjuhIqOD6en6UhqXMdN4QosSo21HeEjCRTGOZ4IsH0GdN0PPfnQ6oUevwgpSf bwUtblcAzEgjaUi1+hUQ16kCZDS+1gy1jecEJ6mIIo6+VNZVzGxF5mxgFeNi6v+q4tYq aA4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KoMrLdBO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j12si5254567pgt.173.2018.02.26.00.21.35; Mon, 26 Feb 2018 00:21:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KoMrLdBO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751735AbeBZIVc (ORCPT + 28 others); Mon, 26 Feb 2018 03:21:32 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:38464 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752221AbeBZIV1 (ORCPT ); Mon, 26 Feb 2018 03:21:27 -0500 Received: by mail-pg0-f68.google.com with SMTP id l24so5913590pgc.5 for ; Mon, 26 Feb 2018 00:21:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=5jc9doNqehmWExc3XoeNI1qQ6N7FZfbJliUkP3bf70M=; b=KoMrLdBO5Qvlzer3bGL6wb3OjGdlnUFwBVM2ez8j7L/6ESku7wqpYdcGQuqw9We4Ce ez9+4SLG3bOA+nwgwLrHIgxYaNuGW8orqigbhAuVJ5LeRHV63c4YF5AxJIGlakLPSfwo MzPzkBM5mi/ffzU+X0863/50ZPYaCiNJks25E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=5jc9doNqehmWExc3XoeNI1qQ6N7FZfbJliUkP3bf70M=; b=MgHnGgbH0iIkHPS/kDH0a82NwVepUg1oEJolIn8F6YH0+GMcbLyHW33AdQlEediPGr 2DZfEv2W48BAWfjiAVsMUZ62VzpDMH5dA21KH7gBsmhRKZ+1+CVu23Y4+WGetcyTrK39 8iU4Fe8Wi+65JjWd+BBtoS3Ovlim02WmSjxP7msKsvWKEyQhP+ii/a+q2VNyhjzkgT8K /V4zkrO9w+jh6IcLJRpqASs0y9XsLBcx7D58cz6pxw1pe5VsYMYtckR6bJGB5yTCos/T WLZPtygtYp/topY1TQbB5fEC2/+HCWuBPv24QMLmV9EVcrtqsR21jCQAMWT8VkI1KPAN gJNQ== X-Gm-Message-State: APf1xPBdpKe60tRQgl8YtU5AnnTisEjPnHNBUNsB8Hn8+RomaOY9A6gM aP+lP541XGsSII9UjrZdtzk6fA== X-Received: by 10.98.226.16 with SMTP id a16mr9691686pfi.157.1519633286699; Mon, 26 Feb 2018 00:21:26 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id o86sm1422706pfi.87.2018.02.26.00.21.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 00:21:26 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 03/52] arm64: barrier: Add CSDB macros to control data-value prediction Date: Mon, 26 Feb 2018 16:19:37 +0800 Message-Id: <1519633227-29832-4-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> References: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon commit 669474e772b9 upstream. For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Alex Shi Conflicts: arch/arm64/include/asm/assembler.h no psb_csync in arch/arm64/include/asm/barrier.h --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.7.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 851290d..8760300 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -87,6 +87,13 @@ .endm /* + * Value prediction barrier + */ + .macro csdb + hint #20 + .endm + +/* * NOP sequence */ .macro nops, num diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 0fe7e43..c68fdc5 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -31,6 +31,8 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define csdb() asm volatile("hint #20" : : : "memory") + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st)