From patchwork Mon Feb 26 08:20:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129583 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3357735lja; Mon, 26 Feb 2018 00:24:51 -0800 (PST) X-Google-Smtp-Source: AH8x224AP3Q4JfTbgaJh937Zw0H6bE0u7KcEGY2HIW8YOjcE2Badg0UdnRFOzybPXim6em8ouq+R X-Received: by 10.98.14.200 with SMTP id 69mr9719269pfo.168.1519633491674; Mon, 26 Feb 2018 00:24:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519633491; cv=none; d=google.com; s=arc-20160816; b=RWYiQAZVdrQHWJBVJ/8jMq7XMpXJRJo7SmPP5m83CQiuUD9cVuODkqTkm96IfROQp6 3SJzTyUvNmo8hdWf0NL2CnPxsBkO2kEgUPAGQOvrPyqDlFlHV/oVH83IYSgzWIwFPb35 xrN/WDsJfo69scNYVAjbhwaWm1UgG+66ucu605hf0ptV7WS/8kGlvfHMfBuyJpCKqK/w Ncnqc6Ofm33sYzAoyU+TKIEVFl0giLsxalVyTdLFbdkL5dIk+dElrSdTxlNM4W4cuS9A lQ4s7XMCLBf2Jjm6s5ASdQXyQnnNc+pjijss0850hi5o68XNG9Kz4QHN+CnIxqdRJkgh 7CHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=LDkUfKYFKhXo5brVfmtfx8nxEICwb5REcDsVergX7aE=; b=jEh7KqiLo9dNy5pUgu2rgPJJ1so72f+HfcHVV5UIembQzJUzW+s7UBvUvh2XbTAxZC Pdh5QwgQZwXteb2kptykU8IksGNZfyE3U1gzTHhIhRxm4aAHlmiR7LjLIqV3/1HjLjz8 AVML6YEkS6xffQ3R11ZUzhzW++A3io/WgfzOOxU2DJ5GP1FjlJb0/azv9yn2K7gFCIRy BfUF2KfYrS/dJoRkS/+8BSEwBSARzUp19relgkdQNO35IqiyMTgbF5nmAd08ZedNrQmq WSmQxAOzY7wxm54Kk28g8CT9f+kG9cKhpB9bciTqjMTN68gyLbUGmJMi2e16aS6BCT4x 3Fhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z+Zttg+b; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si6389538plp.678.2018.02.26.00.24.51; Mon, 26 Feb 2018 00:24:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z+Zttg+b; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752241AbeBZIYs (ORCPT + 28 others); Mon, 26 Feb 2018 03:24:48 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:33339 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751925AbeBZIYe (ORCPT ); Mon, 26 Feb 2018 03:24:34 -0500 Received: by mail-pf0-f194.google.com with SMTP id q13so6223937pff.0 for ; Mon, 26 Feb 2018 00:24:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=LDkUfKYFKhXo5brVfmtfx8nxEICwb5REcDsVergX7aE=; b=Z+Zttg+boqPovLMdmn0u3gkIMcL4DTBIXZ1GnnIg87+EVmNm3t1SfXogG2FwP0G5H3 lL6vmUqc2PP/czCeevJfl1O8HzqwvKMyApJVmjPKaHtYZn+R7A5CGSbBFwwTbwsLL7vp L/rXZfWiVDCAxqOpOqR5a+emsrVxU5O+6gbMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LDkUfKYFKhXo5brVfmtfx8nxEICwb5REcDsVergX7aE=; b=krukydZxDhrFAfs0BXRcWZ5hH3BmKoiY5Nh9gbRv8P0fNzvppYa2J1kNIGw1MIS1P9 dMboBc7aszQRWamFCsge5cqGHngdVSQbKdY7jqfXl4lYbMW6UmgYL1g3suYix1hxBJSK 2lTXlT5RdN5MQ6Mpm5+AatBrFJLr5sUwuExOkK/hZzrHLTG99C+YddeuOpmReOnRQv9x e8BJrtlT9SluqjP3cx2tDyQS0HwKLktTqVusFTMa0/ADIeynr2s+idFipEnRgyjPly8F 4q/BTN8CFIWC0B5Hc8Untyy2ASBA45tUlp3hrhGao1u8aFQaRJRLO2Y3tfUz+owTNwdF SWtQ== X-Gm-Message-State: APf1xPCroYSUCFSmDUr6v1bimolGtJCSfm5O5fB3GTCl1lWHDiP+MpxQ dnHjXD4G4KqmbHn4y2XFyQs+Jg== X-Received: by 10.98.144.65 with SMTP id a62mr9769389pfe.96.1519633473513; Mon, 26 Feb 2018 00:24:33 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id o86sm1422706pfi.87.2018.02.26.00.24.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 00:24:32 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 29/52] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Date: Mon, 26 Feb 2018 16:20:03 +0800 Message-Id: <1519633227-29832-30-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> References: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon commit aa6acde65e03 upstream. Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Alex Shi Conflicts: no falkor in arch/arm64/kernel/cpu_errata.c --- arch/arm64/kernel/bpi.S | 24 ++++++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.7.4 diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index 06a931e..dec95bd 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) +ENTRY(__psci_hyp_bp_inval_start) + sub sp, sp, #(8 * 18) + stp x16, x17, [sp, #(16 * 0)] + stp x14, x15, [sp, #(16 * 1)] + stp x12, x13, [sp, #(16 * 2)] + stp x10, x11, [sp, #(16 * 3)] + stp x8, x9, [sp, #(16 * 4)] + stp x6, x7, [sp, #(16 * 5)] + stp x4, x5, [sp, #(16 * 6)] + stp x2, x3, [sp, #(16 * 7)] + stp x0, x1, [sp, #(16 * 8)] + mov x0, #0x84000000 + smc #0 + ldp x16, x17, [sp, #(16 * 0)] + ldp x14, x15, [sp, #(16 * 1)] + ldp x12, x13, [sp, #(16 * 2)] + ldp x10, x11, [sp, #(16 * 3)] + ldp x8, x9, [sp, #(16 * 4)] + ldp x6, x7, [sp, #(16 * 5)] + ldp x4, x5, [sp, #(16 * 6)] + ldp x2, x3, [sp, #(16 * 7)] + ldp x0, x1, [sp, #(16 * 8)] + add sp, sp, #(8 * 18) +ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0e07893..f8810bf 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -53,6 +53,8 @@ static int cpu_enable_trap_ctr_access(void *__unused) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) { @@ -94,6 +96,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL + static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -118,6 +123,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } + +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #define MIDR_RANGE(model, min, max) \ @@ -211,6 +231,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .def_scope = SCOPE_LOCAL_CPU, .enable = cpu_enable_trap_ctr_access, }, +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, +#endif { } };