From patchwork Mon Feb 26 08:19:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Shi X-Patchwork-Id: 129575 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3357142lja; Mon, 26 Feb 2018 00:23:54 -0800 (PST) X-Google-Smtp-Source: AH8x225Loe0Qz+DFbFyETwWz2QNymYpnDw93Xx2v71FyUmI+AHuqjje0gncHnJiDBlK5r4N/TInv X-Received: by 2002:a17:902:6e0f:: with SMTP id u15-v6mr9660935plk.78.1519633434487; Mon, 26 Feb 2018 00:23:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519633434; cv=none; d=google.com; s=arc-20160816; b=NtfIecZdztr54mZhI0hmmdkUjyjvEr5ywAMfDwEo+2mcjFZH7yBBx8Jat70+I70OA2 zFolu6m5s1gdBFqwFWEHwZmyyOHwNoa5hAZ/jbqZhXqPaHAoH3ku1D0zXP8lwTRJ8E6U lnW4QWED0AGfXp3J+M37uGboqNsupuZlcw/287gmz1OfBZp3BvNWeox6xE4VmMHgKZPp byFKTUQ7W3DPTkHX1HQR4FPdGMP/ZGkhN6/MePHn6pFdFUBgDCAJBhjXuBb7giXco3uU 8ETuxzgNhwfaBRAEEcqnUnx3+jPqaVXBIc+UarN4HN41KokRrAx8y0qY6VXpOT+GOpLK b+pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=vlTjjzmQguibQ42hHx0fE9h4nxyZ4I8LAAjWye+MNJs=; b=EcJxTdsMHRhGoVjx3vDist1rPqdnbwr71pIM43UkSJtGGJbo9hjWGQfL2qoshvtGwY QNgn5ooaZtf/rkDdkDjOFTf+d3+iimu7f6UDtUIAhjDYv8kcWlef7gFoK3CJYyVC6g8N oulEG4XLzGmwGf6ZiRqV8yoPUNEt5rj5QxWCP/JeGJ3F/ravx+QeZ1BmPrMleo2PiCMp XHI+khbC5VrI6j0yDpQysXjuPlFs2DLKNUBpEgA9CxMyrTXc/pDrfb10i9XpsN1VYvJi eCD5dhV1Ezw0xrDHiLUs2/kha4xMFTG6nJMedOmSuXCvzvxCpBHHSy3KXoKEnI18sXVP 6s+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H6XzJ+Lr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x7si6415744pfb.298.2018.02.26.00.23.54; Mon, 26 Feb 2018 00:23:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H6XzJ+Lr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751908AbeBZIXv (ORCPT + 28 others); Mon, 26 Feb 2018 03:23:51 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:41191 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752009AbeBZIXq (ORCPT ); Mon, 26 Feb 2018 03:23:46 -0500 Received: by mail-pf0-f194.google.com with SMTP id f80so1120168pfa.8 for ; Mon, 26 Feb 2018 00:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=vlTjjzmQguibQ42hHx0fE9h4nxyZ4I8LAAjWye+MNJs=; b=H6XzJ+LrfMw30lEmQuML6DlUcJu1aA7EtJTzC3GoVnxPmrxa9iUpyY+8DS1Z0bEIog dPU0d56WZC2pgalAdZ8ZhGfFyJAh3jm2cf5Er8/RzDGWYWvKXL27UlXW7SBUU466fk1m cePvDDJoKWzZ99ITa1PJqQdKFTrqF5wGxNffQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=vlTjjzmQguibQ42hHx0fE9h4nxyZ4I8LAAjWye+MNJs=; b=uc2VrHE7ma90/F/0RtUGwbJ1YP4Oqip943IyfQvXHn4DpT21lXAE4kQBKwCinkSBSO SUtIUaM3AIsm2xOE0Vj8An7YjMXPJl+hb2JOeJuF8gexz8Vg8/LkE8UtvmdWw7/eOpaU NMxIfX2v1ucbgsYrU+ko2/EIUaMMqDF1re59Lmu3GlUREpQisKRbdaSiuN3HeElR7iM+ ATcgtdguSVOimQhZcnqgpew9y/h3MkxCSikpQmxWm+GK2gxRlDWXR7sepFX6gMLeKpD+ /QNfrVkLVypSut7Mqg/5CEdJuL5fWNQN9jgLpX+6xy7PhFd2esZprADK082IlFuPyftT GVxA== X-Gm-Message-State: APf1xPBrEKbQo7Cv80k/UcjQzhBxqoWsbjM/TSM3rQTIZR5V8uZfJZRb nYYsGDoqQBLAejhfsEv+NbUaMg== X-Received: by 10.98.96.70 with SMTP id u67mr9936386pfb.66.1519633425734; Mon, 26 Feb 2018 00:23:45 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id o86sm1422706pfi.87.2018.02.26.00.23.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 00:23:45 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 22/52] arm64: Move post_ttbr_update_workaround to C code Date: Mon, 26 Feb 2018 16:19:56 +0800 Message-Id: <1519633227-29832-23-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> References: <1519633227-29832-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier commit 95e3de3590e3 upstream. We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Alex Shi Conflicts: don't include PAN related changes arch/arm64/include/asm/assembler.h arch/arm64/kernel/entry.S arch/arm64/mm/proc.S --- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 2 files changed, 10 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index efcf1f7..32eeabe91 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -224,6 +224,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c2adb0c..cca061a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -136,8 +136,7 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb - post_ttbr0_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"