From patchwork Mon Feb 19 19:13:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128842 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3801660ljc; Mon, 19 Feb 2018 10:23:38 -0800 (PST) X-Google-Smtp-Source: AH8x224eWDbqNxdVg8YNfVbfUEZs8VrkbVSGexvrbr9PnM9ljK8ET+2QuQaO9Hkt3FXb/1Z2qxIB X-Received: by 2002:a17:902:34a:: with SMTP id 68-v6mr15282872pld.276.1519064618479; Mon, 19 Feb 2018 10:23:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519064618; cv=none; d=google.com; s=arc-20160816; b=vT23DodIqh2pEAlrGnK/tWja1DeQ9rWdxPyWoc5FKuyA11iKmzPTDvszuspfxIBvyt TngHStxwQ3iQmFBNBPWSR2iOv8K0NDzPlBeVmE5c/oaBFANot+28UXzg+JMLyZLtlxUL MslUgIOe6A6dqJ+01aCKFN58PstPCcxhBKGoq4rA5doKR699S1ViV2J8QilOEX2SGQ5G 2gwaUEPurzHyo8zcgXkaO0iRsFDCMytZXxGjgQWy72F1O4GMbc8RNoYObXMb+01lf7fF Xl2hFhnzuknC8Hfs7gFkVcatoIaEBZoRigDTv5SG0RjnCAIJKTipJY4Y0Tok20ajGRya g5Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/CrMue9HbsBxIV0jPmPgeYRWQedTXlzLHFlymRVa1qI=; b=ov3H3h8iiIQhJ0wX0bqJ6mt4O+n4cVwBxD0yx7j7wc+JWDu45FlhSA8e3eR8kZ63g2 cvN7AnNAl+6UAt/cy4CGrBR/8IbWYsz+mKMNiVgpZo+Vh1jfE1N1N16nmVYc+nF7QdZR CqEV7UCSztEYNn+kEqzhfzTbFRmrCo5nlOQLwkZmMH6GGJjuxykfhqkD7ScVaebvLutT 2jLaEgLn1HqBO4loiM+9N3ItY2BCDsg2uuuqG4GpvA+wTIlZaU3NzMT3g6GatxcdlDtR Rmkk6hH2bl/hXz7sectwG5tz/dHSDyCXHWOm3zhGHLaVmSBlLTzEqymln42wwjeVlqkJ tFDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i11si3508430pgq.332.2018.02.19.10.23.38; Mon, 19 Feb 2018 10:23:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753704AbeBSSXf (ORCPT + 28 others); Mon, 19 Feb 2018 13:23:35 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5252 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753434AbeBSSWQ (ORCPT ); Mon, 19 Feb 2018 13:22:16 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 183041E528CCC; Tue, 20 Feb 2018 02:22:00 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Tue, 20 Feb 2018 02:21:52 +0800 From: John Garry To: , , , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 2/8] scsi: hisi_sas: support the property of signal attenuation for v2 hw Date: Tue, 20 Feb 2018 03:13:25 +0800 Message-ID: <1519067611-206638-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519067611-206638-1-git-send-email-john.garry@huawei.com> References: <1519067611-206638-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The register SAS_PHY_CTRL is configured according to signal quality. The signal quality is calculated by signal attenuation of hardware physical link. It may be different for different PCB layout. So, in order to give better support to new board, this patch add support to reading the devicetree property, signal-attenuation. Of course, we still keep an default value in driver to adapt old board. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 4ccb61e..ab6db50 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -406,6 +406,17 @@ struct hisi_sas_err_record_v2 { __le32 dma_rx_err_type; }; +struct signal_attenuation_s { + u32 de_emphasis; + u32 preshoot; + u32 boost; +}; + +struct sig_atten_lu_s { + const struct signal_attenuation_s *att; + u32 sas_phy_ctrl; +}; + static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), @@ -1130,9 +1141,16 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) } } +static const struct signal_attenuation_s x6000 = {9200, 0, 10476}; +static const struct sig_atten_lu_s sig_atten_lu[] = { + { &x6000, 0x3016a68 }, +}; + static void init_reg_v2_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; + u32 sas_phy_ctrl = 0x30b9908; + u32 signal[3]; int i; /* Global registers init */ @@ -1176,9 +1194,28 @@ static void init_reg_v2_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); + /* Get sas_phy_ctrl value to deal with TX FFE issue. */ + if (!device_property_read_u32_array(dev, "signal-attenuation", + signal, ARRAY_SIZE(signal))) { + for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) { + const struct sig_atten_lu_s *lookup = &sig_atten_lu[i]; + const struct signal_attenuation_s *att = lookup->att; + + if ((signal[0] == att->de_emphasis) && + (signal[1] == att->preshoot) && + (signal[2] == att->boost)) { + sas_phy_ctrl = lookup->sas_phy_ctrl; + break; + } + } + + if (i == ARRAY_SIZE(sig_atten_lu)) + dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n"); + } + for (i = 0; i < hisi_hba->n_phy; i++) { hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); - hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); + hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl); hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0); hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);