From patchwork Tue Feb 6 17:44:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127047 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096898ljc; Tue, 6 Feb 2018 09:00:40 -0800 (PST) X-Google-Smtp-Source: AH8x2245ehX+HatFFVenRT5nkKtw4aDRuALU4/9jO/glf6U1WmIAzjqghO7tO45RvR8gBuQaQoRH X-Received: by 10.99.149.4 with SMTP id p4mr1048894pgd.0.1517936440173; Tue, 06 Feb 2018 09:00:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936440; cv=none; d=google.com; s=arc-20160816; b=YRS3yPlRFqE0CJbmntwCd0/K9N3kJEVxhkfrc3bX6q1AjGJzrsNad7EBxQbEiDfrks yUs821z4VfAN2KxPSYg8/TKN4nqRVXn3RcS/OGpFn6kgA8+zbCBGTJqOK+qP0mXCQyLw HVhly21B/ZZPByvbgtLF94qrHskR2LOFKIW4S/Rdj24+kIRvlRvolWQv+4RnxcKEVav1 rQM3slJy8cAr0fA4aVlynT97JmNSmaAXFsLgP3va4nktabAjlmrP4EQDvzDckAWfoWsh Pkzjif9w+hhLpWgXIalgpvwKmnsXAfHqPm2arii4qyExVGaGkYy0D4u2J7ZQqvrlnUj6 n54g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=JajFpS6VEwLGJ8U9cchmSwUR4q7hAK4USYb+7nb7Gpc=; b=tZf3J2zsBVSAJXsvosPIcQnPYGTjhcT+RnDU3bRQNeZa9YlxMt1KeaVqbrOxpzRZjV 0tXK62M5AS26D6I4Tx431SoKdNiFDdXhARAOGUvJyxCSx10ID7u1dmQcAdrQk4DlvHQA z5aZHDODAeciEt4sEFCLHHZ5lIwDYtVKnQzFaBQNG3ZR5ZuJrltefaKjEkncobcuFZ+F PJ2smJMyWk69/hu3YGNaF559XjGRaCNg0m11D0lxkNcpoBLlm+v+n2AKvSIIt4mMhCuw BTA3uNlgaAZJmW5ukGDnKkvrdz1EhhcsQFy0U1zuaUIBMIGqZzJ2lZCmhwhHzLRykD/e DXsg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18-v6si1544992plq.228.2018.02.06.09.00.39; Tue, 06 Feb 2018 09:00:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753250AbeBFRAh (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:37 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51640 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753141AbeBFQ4C (ORCPT ); Tue, 6 Feb 2018 11:56:02 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 84AF3B2D1190B; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:51 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 4/9] perf vendor events arm64: Relocate Cortex A53 JSONs Date: Wed, 7 Feb 2018 01:44:59 +0800 Message-ID: <1517939104-230881-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The arm64 pmu-events folder structure has become disorganised, since now we have core and also vendor folders at the same level folder. Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm vendor subdirectory. Signed-off-by: John Garry --- .../arch/arm64/arm/cortex-a53/branch.json | 27 +++++++++++ .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/cache.json | 27 +++++++++++ .../arch/arm64/arm/cortex-a53/memory.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/other.json | 32 +++++++++++++ .../arch/arm64/arm/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++ .../pmu-events/arch/arm64/cortex-a53/branch.json | 27 ----------- .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/cache.json | 27 ----------- .../pmu-events/arch/arm64/cortex-a53/memory.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/other.json | 32 ------------- .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ---------------------- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 13 files changed, 183 insertions(+), 183 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json new file mode 100644 index 0000000..3b62087 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0x7A", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed - Indirect branch" + }, + {, + "EventCode": "0xC9", + "EventName": "BR_COND", + "BriefDescription": "Conditional branch executed" + }, + {, + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MISPRED", + "BriefDescription": "Indirect branch mispredicted" + }, + {, + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_MISPRED_ADDR", + "BriefDescription": "Indirect branch mispredicted because of address miscompare" + }, + {, + "EventCode": "0xCC", + "EventName": "BR_COND_MISPRED", + "BriefDescription": "Conditional branch mispredicted" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json new file mode 100644 index 0000000..11baad6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" + }, + {, + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" + }, + {, + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" + }, + {, + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" + }, + {, + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json new file mode 100644 index 0000000..73a2240 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -0,0 +1,32 @@ +[ + {, + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + }, + {, + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + }, + {, + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" + }, + {, + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + }, + {, + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + }, + {, + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json new file mode 100644 index 0000000..3149fb9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -0,0 +1,52 @@ +[ + {, + "EventCode": "0xC7", + "EventName": "STALL_SB_FULL", + "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" + }, + {, + "EventCode": "0xE0", + "EventName": "OTHER_IQ_DEP_STALL", + "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" + }, + {, + "EventCode": "0xE1", + "EventName": "IC_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" + }, + {, + "EventCode": "0xE2", + "EventName": "IUTLB_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" + }, + {, + "EventCode": "0xE3", + "EventName": "DECODE_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" + }, + {, + "EventCode": "0xE4", + "EventName": "OTHER_INTERLOCK_STALL", + "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" + }, + {, + "EventCode": "0xE5", + "EventName": "AGU_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" + }, + {, + "EventCode": "0xE6", + "EventName": "SIMD_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." + }, + {, + "EventCode": "0xE7", + "EventName": "LD_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" + }, + {, + "EventCode": "0xE8", + "EventName": "ST_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json deleted file mode 100644 index 3b62087..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" - }, - {, - "EventCode": "0xC9", - "EventName": "BR_COND", - "BriefDescription": "Conditional branch executed" - }, - {, - "EventCode": "0xCA", - "EventName": "BR_INDIRECT_MISPRED", - "BriefDescription": "Indirect branch mispredicted" - }, - {, - "EventCode": "0xCB", - "EventName": "BR_INDIRECT_MISPRED_ADDR", - "BriefDescription": "Indirect branch mispredicted because of address miscompare" - }, - {, - "EventCode": "0xCC", - "EventName": "BR_COND_MISPRED", - "BriefDescription": "Conditional branch mispredicted" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json deleted file mode 100644 index 11baad6..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" - }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" - }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" - }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" - }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json deleted file mode 100644 index 73a2240..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json +++ /dev/null @@ -1,32 +0,0 @@ -[ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" - }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" - }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" - }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" - }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" - }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json deleted file mode 100644 index 3149fb9..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json +++ /dev/null @@ -1,52 +0,0 @@ -[ - {, - "EventCode": "0xC7", - "EventName": "STALL_SB_FULL", - "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" - }, - {, - "EventCode": "0xE0", - "EventName": "OTHER_IQ_DEP_STALL", - "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" - }, - {, - "EventCode": "0xE1", - "EventName": "IC_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" - }, - {, - "EventCode": "0xE2", - "EventName": "IUTLB_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" - }, - {, - "EventCode": "0xE3", - "EventName": "DECODE_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" - }, - {, - "EventCode": "0xE4", - "EventName": "OTHER_INTERLOCK_STALL", - "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" - }, - {, - "EventCode": "0xE5", - "EventName": "AGU_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" - }, - {, - "EventCode": "0xE6", - "EventName": "SIMD_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." - }, - {, - "EventCode": "0xE7", - "EventName": "LD_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" - }, - {, - "EventCode": "0xE8", - "EventName": "ST_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 952a05c..cf14e23 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core -0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core