From patchwork Fri Jan 12 00:46:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 124255 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1437568qgn; Thu, 11 Jan 2018 17:00:40 -0800 (PST) X-Google-Smtp-Source: ACJfBoscM5FKiHvMkVK6RL3xUQrYylTBSWcDAUpGD1t38SRs7QNDX93QbPA9W/a800G/ECsL1y32 X-Received: by 10.98.61.208 with SMTP id x77mr16973729pfj.2.1515718840488; Thu, 11 Jan 2018 17:00:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515718840; cv=none; d=google.com; s=arc-20160816; b=trLm3cLRrgXJF0q+4DtTLc7rnB7Cz2cFW0+2v6Aq3rTuq2TxnSaAGiZEg/IpT2agfg Sjk0AUF2m8QulODUC0mJgP/6U/DdjlhshKWyENS8NZ+riXIh6bH1gsZMmLvhu8OpYpr9 jTpG4MB6cpRUMfcOeM7hHpK7oOyPWdxwkhi6zhKtL5GsUVytf/0vrLTrD5x9lpOScMwz jDqCtL27jOHNR1AtNCWqFb7wp8GerHlQm10SWFFHkpZ5tPhXIr7xJqCHdN8FW1qmdqsT HQjL8DOjPjkl+30rPFuO1TtYsntj3yWRi5b6WCNG8kYReBJpW0EhRB32E4nf3fB+LT3K lC/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:cc:to:from :subject:arc-authentication-results; bh=BkLGLtbQW9bkVucVMp86LgsUzo6h0NgEkcJYYjlhOM4=; b=ZAmM70/QRuZNlB/Rup+sqxt5nL5tCie6OVvGp6jJx/3kvzOplsEBOn6kmO9iQF+rrx i8D8Q0qFnBv0XnjS7m8YCxh+tsku9A4GsFfcOqh1VbB7/pyz841E3MIP+e7y4sGXDeFo uB5UdnRZZpEgD5QgB9T872Pc5yBOfPU9UEsolaMZQmk6L1K6MbvlcowirArKGwtKXlDb SLYsLYsx6mIkx+ESKM6k9ramMsklG4dSERrYKkhgFw0+f2vs6CLwEv1j8Lr5yGpVkkNy MuFVV2APh/vl1PHo28RanuvohhxWGvzQcuFZ3fosx/+qbixAij7yPfrAHXbtl237jc/l 8G6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y20si12800228pgv.215.2018.01.11.17.00.40; Thu, 11 Jan 2018 17:00:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933432AbeALBAi (ORCPT + 28 others); Thu, 11 Jan 2018 20:00:38 -0500 Received: from mga01.intel.com ([192.55.52.88]:23328 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932685AbeALAyz (ORCPT ); Thu, 11 Jan 2018 19:54:55 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jan 2018 16:54:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,346,1511856000"; d="scan'208";a="193156924" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.16]) by orsmga005.jf.intel.com with ESMTP; 11 Jan 2018 16:54:54 -0800 Subject: [PATCH v2 03/19] arm: implement ifence_array_ptr() From: Dan Williams To: linux-kernel@vger.kernel.org Cc: Mark Rutland , linux-arch@vger.kernel.org, kernel-hardening@lists.openwall.com, tglx@linutronix.de, torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@linux.intel.com Date: Thu, 11 Jan 2018 16:46:40 -0800 Message-ID: <151571800075.27429.5000616446434113763.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <151571798296.27429.7166552848688034184.stgit@dwillia2-desk3.amr.corp.intel.com> References: <151571798296.27429.7166552848688034184.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.17.1-9-g687f MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Rutland This patch implements ifence_array_ptr() for arm, using an LDR+MOVCS+CSDB sequence to inhibit speculative use of the returned value. Signed-off-by: Mark Rutland Signed-off-by: Dan Williams --- arch/arm/include/asm/barrier.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 40f5c410fd8c..919235ed6e68 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -59,6 +59,30 @@ extern void arm_heavy_mb(void); #define dma_wmb() barrier() #endif +#define ifence_array_ptr(arr, idx, sz) \ +({ \ + typeof(&(arr)[0]) __nap_arr = (arr); \ + typeof(idx) __nap_idx = (idx); \ + typeof(sz) __nap_sz = (sz); \ + \ + unsigned long __nap_ptr = (unsigned long)__nap_arr + \ + sizeof(__nap_arr[0]) * idx; \ + \ + asm volatile( \ + " cmp %[i], %[s]\n" \ + " bcs 1f\n" \ + " ldr %[p], %[pp]\n" \ + "1: movcs %[p], #0\n" \ + " .inst 0xe320f018 @ CSDB\n" \ + : [p] "=&r" (__nap_ptr) \ + : [pp] "m" (__nap_ptr), \ + [i] "r" ((unsigned long)__nap_idx), \ + [s] "r" ((unsigned long)__nap_sz) \ + : "cc"); \ + \ + (typeof(&(__nap_arr)[0]))__nap_ptr; \ +}) + #define __smp_mb() dmb(ish) #define __smp_rmb() __smp_mb() #define __smp_wmb() dmb(ishst)