From patchwork Mon Jan 8 17:32:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123767 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3010907qgn; Mon, 8 Jan 2018 09:41:57 -0800 (PST) X-Google-Smtp-Source: ACJfBotVhCmLRK1h/fVLduZWZpGWaU59cYb5jQQZJaZHybDNGKVo1PcpYcMSm9W9BjaTJs3/5qUV X-Received: by 10.99.165.80 with SMTP id r16mr9351307pgu.73.1515433317341; Mon, 08 Jan 2018 09:41:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515433317; cv=none; d=google.com; s=arc-20160816; b=kK8rIkc+8eMJp2Fs/qGqr9+1PJCllx7fxeq1OewlWP6x3J2oqw3ZLErosFFPd2OsHR boIsJ75KsPWXqWImqXIyhMNVsgYMvufac8qZw+5yZFfJ9yO3q9M/dBC484t+mNXT2v8O xOhV5VIJdDHUynpsZBWcIDsjk3WDSbCEDMMK2B/U5o+zhEpReHdg8of27OWiv4fKzXyO n34RYUOwG+91ZUEdL+X5zOorHBRTL145dioLqU1KJwHviKVNflEgMHxVlcXNir/6StG3 PoUkfIA+oKpVanrTOvs9Vxm+fFAIn+OBUowdBHj0nwPEIHU4JOCe+dE75Sq27kk2kq5P u+4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=nEHIR36Mf5u3g64C59nM3eCdDzVcRkURBdphV8mbT2I=; b=DeBIg/2ttA4W2WywI4PvZzdxVgQSkYXhXEmNbOGcly9lZbdoFz42YZThl1vg9R5eFO PPvlxUiaMqDJ4jT2ixn0wLYiGxu9QXXn+0Kt2fD9OUBwdqdgW5YSBXiTjgJ+0hSw3WVZ zj3FwZS0W91M7I1O7g804AdH1G9GXj8HVa5HtR4P1h+sDXxEXiLSvSJ9K77BZaRKO5bJ gsWOHjCcX5kksjbIec/ZGfWWUy5+rBi7zpTWSOoWpVV+glnBuiZYYM+Li1A+3HYXtksu xtdKcWnRcK3Crh7KXi6/n6Sv3gYeOi/g1nFixk4esAwDF2uEzl/N8qIYIp1G0EH+6Twc QBUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m66si8689189pfj.294.2018.01.08.09.41.56; Mon, 08 Jan 2018 09:41:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754564AbeAHRek (ORCPT + 28 others); Mon, 8 Jan 2018 12:34:40 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42946 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754312AbeAHRck (ORCPT ); Mon, 8 Jan 2018 12:32:40 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 60E6D19F6; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 331233F5C1; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id BAAB91AE30BB; Mon, 8 Jan 2018 17:32:41 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 13/13] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Mon, 8 Jan 2018 17:32:38 +0000 Message-Id: <1515432758-26440-14-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com> References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jayachandran C Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.1.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 84385b94e70b..cce5735a677c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -89,6 +89,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -102,6 +103,8 @@ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #ifndef __ASSEMBLY__