From patchwork Mon Jan 8 17:32:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123757 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3003389qgn; Mon, 8 Jan 2018 09:34:47 -0800 (PST) X-Google-Smtp-Source: ACJfBotZWVChqXwb7iSp2/Fjok3K8lckAXFGks1AF3Kit/DAitutTkbxIBz7MOacIFG4iwx3ElD2 X-Received: by 10.99.176.9 with SMTP id h9mr620661pgf.448.1515432886991; Mon, 08 Jan 2018 09:34:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515432886; cv=none; d=google.com; s=arc-20160816; b=GgjopdHvJlEatJ/1WiNrBDxoZ3YRAhkp5g/nnB3oXzRN/WXT63RkJPLL88pThrIznL 2TmgP+7Sh48dCJufI9goDVExA6VLrK9u4Q1Uj++XdMEzeOCZ0h8Yax+p9CkxB/7h3kd3 AmxfGR+BjM0pwF9JUoukQGz0dVtiW2cT7XOVxh5/qUPdNmt3IpCSW55kNTbqoqwuRYxQ lLiOIBqb6mW03mudWqvjiiBLdEgdQPuVYHUQMjUA935rT0iJlAtDxTJlsMMbZEvFYjiI 2OcMFZMJTxNNKtUisdXBVB/WwA2CfUVzX1iluRIFFZpIlctumJpXf4gL+QKBWWwo8AkH /RJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=k57UT8HexmdkS25g/RlN/MZjOLlgobpsQLo3ajoplRk=; b=Gy5fHitCYagh1/doV+90RYJjrgkJvePpnGlHOjv8JJAnul0C/e3Y60PwNaI9hqMwpg YzqrE9GM/hbTn/l/lH+gjVPnkv2y6a3J3gRAaNErBxY//N9TlQXw/sdRksmatbhUdLBz i83/RB3Nd4jtT1yJAyqzhKV6uF0/5Sa9/I+I8C56BGtqcTnisvcPEOuR6wm4bYaupGO1 2Yrip2sJjdXeeB1MIQmanmvyk9rEJzXWkOEwfgGIh2RuM/y+gvpQ5ZDKSXUTQlQnRDaQ ZT9uUFDK8RaSCMzgOXBlxE7kJz1OTrYFpoamQRpLtVW3TZrRRydY+LN71BO/4vyHDAKP BAfA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t8si2669499plr.86.2018.01.08.09.34.46; Mon, 08 Jan 2018 09:34:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754622AbeAHRep (ORCPT + 28 others); Mon, 8 Jan 2018 12:34:45 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754309AbeAHRck (ORCPT ); Mon, 8 Jan 2018 12:32:40 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F1EB19CC; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 213E33F487; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9A1921AE304C; Mon, 8 Jan 2018 17:32:41 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 11/13] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Date: Mon, 8 Jan 2018 17:32:36 +0000 Message-Id: <1515432758-26440-12-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com> References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/kernel/bpi.S | 24 ++++++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.1.4 Signed-off-by: Suzuki K Poulose Acked-by: Marc Zyngier diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index 06a931eb2673..dec95bd82e31 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) +ENTRY(__psci_hyp_bp_inval_start) + sub sp, sp, #(8 * 18) + stp x16, x17, [sp, #(16 * 0)] + stp x14, x15, [sp, #(16 * 1)] + stp x12, x13, [sp, #(16 * 2)] + stp x10, x11, [sp, #(16 * 3)] + stp x8, x9, [sp, #(16 * 4)] + stp x6, x7, [sp, #(16 * 5)] + stp x4, x5, [sp, #(16 * 6)] + stp x2, x3, [sp, #(16 * 7)] + stp x0, x1, [sp, #(16 * 8)] + mov x0, #0x84000000 + smc #0 + ldp x16, x17, [sp, #(16 * 0)] + ldp x14, x15, [sp, #(16 * 1)] + ldp x12, x13, [sp, #(16 * 2)] + ldp x10, x11, [sp, #(16 * 3)] + ldp x8, x9, [sp, #(16 * 4)] + ldp x6, x7, [sp, #(16 * 5)] + ldp x4, x5, [sp, #(16 * 6)] + ldp x2, x3, [sp, #(16 * 7)] + ldp x0, x1, [sp, #(16 * 8)] + add sp, sp, #(8 * 18) +ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 16ea5c6f314e..cb0fb3796bb8 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -53,6 +53,8 @@ static int cpu_enable_trap_ctr_access(void *__unused) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) { @@ -94,6 +96,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL + static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -118,6 +123,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } + +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #define MIDR_RANGE(model, min, max) \ @@ -261,6 +281,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), }, #endif +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, +#endif { } };