From patchwork Mon Jan 8 17:32:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123758 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3003422qgn; Mon, 8 Jan 2018 09:34:47 -0800 (PST) X-Google-Smtp-Source: ACJfBouzWJyWvIhShZZMNFRa3Vz2urGB2fmn82Zgb5VBSeFh5Jhk/oj9zYCJXmUch2qcXpHPOy32 X-Received: by 10.99.43.137 with SMTP id r131mr10005876pgr.205.1515432887759; Mon, 08 Jan 2018 09:34:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515432887; cv=none; d=google.com; s=arc-20160816; b=0GhV08joZ7jn3dxmwt665FvHFRMStBDJzRRX8bLMQ2NwCXe5EQDGtOdkYH7f0nl09f 6M15TZ08q2N2PovQXNstGBdVUKpGdqrrCBtaayYcMcXg3kQea8bMlQY7DMSicju0Eybf iDbmlAlV20M88LZg0BKQ7B/rpITjq/AWeU3i+fjZlu+X82UuBbx0kWNDjizj/B2HKrRY ASnhBXbDqiIxiUo6QsQYh3cJWUVYxz8ZmIDCqdKk0iLbDxXWZWhEyDPIPQiVzXTxgH3a Hnj9jA8sAehWe4XQQsg9KSihc2zOyYP7h6CC3NT2RWCFo06a1br482f9a9/EAbcrlLt3 cqUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jpUYmNEx7VU+s0l/ndx3SHVIXhCGbNw/RkyqJRiZOVc=; b=hB2TBQ11LabaoxW171OVKal7ALlFczOVICSwxD81uA6apBWEHJrmbdrJucOA+3n3M/ VemNBKrUJTRbWIjl4cIFYfwVYNsPTL3w+vNCkRCalYdbSlNmJx2XlcmAAJsG7VpLdUK1 AyBgDwpNKUTYAZcHxCq9ltcujxGDhTze6ho3Au8kogTAb79c34MrRvG+xfRg0GRp+30T wU7R5uj7VSmRfviKVca44FStbziE5ZP+BlaMWiw2YJjv3qOCtYvifmmAYAp3BvrwpacC joa4zdyRw/GAfcDD1VUdpyTsTGaDd4mkoF03cTh8aCaM722NJBIZNUDP6+/u/oA8Bz30 Z4Hg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t8si2669499plr.86.2018.01.08.09.34.47; Mon, 08 Jan 2018 09:34:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754637AbeAHReq (ORCPT + 28 others); Mon, 8 Jan 2018 12:34:46 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42928 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754305AbeAHRck (ORCPT ); Mon, 8 Jan 2018 12:32:40 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 46AE616EA; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 184033F7C7; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 89D441AE300C; Mon, 8 Jan 2018 17:32:41 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 10/13] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Mon, 8 Jan 2018 17:32:35 +0000 Message-Id: <1515432758-26440-11-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com> References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.1.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d98261..84385b94e70b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -79,8 +79,10 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 @@ -94,7 +96,9 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)