[v3,09/13] arm64: KVM: Make PSCI_VERSION a fast path

Message ID	1515432758-26440-10-git-send-email-will.deacon@arm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Will Deacon <will.deacon@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon <will.deacon@arm.com> Subject: [PATCH v3 09/13] arm64: KVM: Make PSCI_VERSION a fast path Date: Mon, 8 Jan 2018 17:32:34 +0000 Message-Id: <1515432758-26440-10-git-send-email-will.deacon@arm.com> In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com> References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	arm64 kpti hardening and variant 2 workarounds \| expand [v3,00/13] arm64 kpti hardening and variant 2 workarounds [v3,01/13] arm64: use RET instruction for exiting the trampoline [v3,02/13] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry [v3,03/13] arm64: Take into account ID_AA64PFR0_EL1.CSV3 [v3,04/13] arm64: cpufeature: Pass capability structure to ->enable callback [v3,05/13] drivers/firmware: Expose psci_get_version through psci_ops structure [v3,06/13] arm64: Move post_ttbr_update_workaround to C code [v3,07/13] arm64: Add skeleton to harden the branch predictor against aliasing attacks [v3,08/13] arm64: KVM: Use per-CPU vector when BP hardening is enabled [v3,09/13] arm64: KVM: Make PSCI_VERSION a fast path [v3,10/13] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 [v3,11/13] arm64: Implement branch predictor hardening for affected Cortex-A CPUs [v3,12/13] arm64: Implement branch predictor hardening for Falkor [v3,13/13] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

Message ID

1515432758-26440-10-git-send-email-will.deacon@arm.com

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New

Headers

Received-SPF: pass (google.com: best guess record for domain of
	linux-kernel-owner@vger.kernel.org designates 209.132.180.67
	as permitted sender) client-ip=209.132.180.67; 
From: Will Deacon <will.deacon@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org,
	marc.zyngier@arm.com, lorenzo.pieralisi@arm.com,
	christoffer.dall@linaro.org, linux-kernel@vger.kernel.org,
	shankerd@codeaurora.org, jnair@caviumnetworks.com,
	Will Deacon <will.deacon@arm.com>
Subject: [PATCH v3 09/13] arm64: KVM: Make PSCI_VERSION a fast path
Date: Mon,  8 Jan 2018 17:32:34 +0000
Message-Id: <1515432758-26440-10-git-send-email-will.deacon@arm.com>
In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com>
References: <1515432758-26440-1-git-send-email-will.deacon@arm.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Series

arm64 kpti hardening and variant 2 workarounds | expand

Commit Message

Will Deacon Jan. 8, 2018, 5:32 p.m. UTC

From: Marc Zyngier <marc.zyngier@arm.com>


For those CPUs that require PSCI to perform a BP invalidation,
going all the way to the PSCI code for not much is a waste of
precious cycles. Let's terminate that call as early as possible.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Signed-off-by: Will Deacon <will.deacon@arm.com>

---
 arch/arm64/kvm/hyp/switch.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

-- 
2.1.4

diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 8d4f3c9d6dc4..4d273f6d0e69 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -17,6 +17,7 @@ 
 
 #include <linux/types.h>
 #include <linux/jump_label.h>
+#include <uapi/linux/psci.h>
 
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
@@ -341,6 +342,18 @@  int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 	if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
 		goto again;
 
+	if (exit_code == ARM_EXCEPTION_TRAP &&
+	    (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC64 ||
+	     kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC32) &&
+	    vcpu_get_reg(vcpu, 0) == PSCI_0_2_FN_PSCI_VERSION) {
+		u64 val = PSCI_RET_NOT_SUPPORTED;
+		if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
+			val = 2;
+
+		vcpu_set_reg(vcpu, 0, val);
+		goto again;
+	}
+
 	if (static_branch_unlikely(&vgic_v2_cpuif_trap) &&
 	    exit_code == ARM_EXCEPTION_TRAP) {
 		bool valid;

[v3,09/13] arm64: KVM: Make PSCI_VERSION a fast path

Commit Message

Patch