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[209.132.180.67]) by mx.google.com with ESMTP id b31si8613527plb.613.2018.01.08.05.30.04; Mon, 08 Jan 2018 05:30:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GU9e0XDx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933453AbeAHNaC (ORCPT + 28 others); Mon, 8 Jan 2018 08:30:02 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:39151 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933434AbeAHNaA (ORCPT ); Mon, 8 Jan 2018 08:30:00 -0500 Received: by mail-wm0-f66.google.com with SMTP id i11so14201154wmf.4 for ; Mon, 08 Jan 2018 05:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m1H2f7beiH31JuAk86AoPNEnMD6CLJANQrwsbZWl3bk=; b=GU9e0XDxOWOMGnW9ZU5nWTspHyghUVoS4T2Rl1+IMVls8VGfL0sTmNtpKa5aiZ5mrL hHZRBvrIAgtFSdwJP95L3UGoK8S9iyk7I/E1lYu4epbNkWaqQvg5SDqPCe4VuiNTNbvF 5Eex1hk2DZdTj23PR6Seor1O8yjiSFq7cVGTw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m1H2f7beiH31JuAk86AoPNEnMD6CLJANQrwsbZWl3bk=; b=nrYGJiDtJ/tgqqG929IAfT7WA6155Gg8UVDgHddwSzGBNipF5wNeDSdV/GpApRVnnb 5c4ETpiJSvpx05R/pfxWnA04Sy/PbUjMnOkSBrHi+dk1nV305eqDlbYcGfxrKlf/maUj YcF4FfGZ7KB8ocP0H0VSOqxlpiukKx2K/rnexFeE34e9UtVBKWrsFN91+DnU6dU12tFz wK6bUYf+LBhsN50VYAW6CImpx5WiS9yT7EwxV4b/vZ9KspDx3Pnr99DWjMAM+1qzAreu szROypokKMmzBm+K5liTrs3q8Dq2jkUrQOSykw4Uyai662YrRo2AOQO6I8zQQKw9blUY hC9Q== X-Gm-Message-State: AKGB3mIIrfHtIwerl6wbAblwjhKDeGvV6tlumZuSrDKbQP+XVv0yiGPO JzAnFCjYV2E1w1C7GM9NLYKCXw== X-Received: by 10.28.128.83 with SMTP id b80mr10041445wmd.41.1515418199098; Mon, 08 Jan 2018 05:29:59 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:58 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 20/20] clocksource/drivers/stm32: Start the timer's counter sooner Date: Mon, 8 Jan 2018 14:28:59 +0100 Message-Id: <1515418139-23276-20-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As we have a lot of timers on this platform, we can have potentially all the timers enabled in the DT, so we don't want to start the timer for every probe otherwise they will be running for nothing as only one will be used. Start the timer only when setting the mode or when the clocksource is enabled. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index dcf8445..4ce2345 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -101,7 +101,15 @@ static void stm32_clock_event_disable(struct timer_of *to) writel_relaxed(0, timer_of_base(to) + TIM_DIER); } -static void stm32_clock_event_enable(struct timer_of *to) +/** + * stm32_timer_start - Start the counter without event + * @to: a timer_of structure pointer + * + * Start the timer in order to have the counter reset and start + * incrementing but disable interrupt event when there is a counter + * overflow. By default, the counter direction is used as upcounter. + */ +static void stm32_timer_start(struct timer_of *to) { writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); } @@ -137,7 +145,7 @@ static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); } @@ -146,7 +154,7 @@ static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return 0; } @@ -235,6 +243,13 @@ static int __init stm32_clocksource_init(struct timer_of *to) * sched_clock. */ if (bits == 32 && !stm32_timer_cnt) { + + /* + * Start immediately the counter as we will be using + * it right after. + */ + stm32_timer_start(to); + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name);