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[209.132.180.67]) by mx.google.com with ESMTP id r4si7437553pgp.779.2018.01.08.05.31.13; Mon, 08 Jan 2018 05:31:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8W0dFPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933498AbeAHNbL (ORCPT + 28 others); Mon, 8 Jan 2018 08:31:11 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:39310 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933408AbeAHN34 (ORCPT ); Mon, 8 Jan 2018 08:29:56 -0500 Received: by mail-wr0-f194.google.com with SMTP id z48so5014846wrz.6 for ; Mon, 08 Jan 2018 05:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zvaTTcfXtuzr1lD0vuoooMntsEE/356EFRYm5/iSR3U=; b=P8W0dFPOT+qQ0FriyOGe08cIwBV4dKMIiGpr4mLBrazuA9g9Kmq/CHsPW8TL3EIi8K Cs98WQdH/8qMwH2xNrNRetElGhskT79ApAQSIMpxrrtKUzIlC5mKnN9yg7mN/KerMcfT uelZafb+Vg9oMV0JD3pYghFbHd5JGuXFZ0Ce0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zvaTTcfXtuzr1lD0vuoooMntsEE/356EFRYm5/iSR3U=; b=HSaR16b5d6iBfmkpGYa8JQp5+DUyeE7eQgpSSJEa1ZhSUZ8F7NZB33d3kSlLCKbZJX KAYgTpuW/HD/DWpjsv/GLqvnz3UFR3jAbownW/HSW2O5cUZC4zN0BY77ohIyn9dQaaCM 3mM4cmPvyuXk9BAx8v8p/PVRjsFQ/C1pl6y4skJoGox9GOc7TrmSo+C1PS1u7iw4vIwF XIgqLUFS2YjuF4HDtO+0YAXJF6/qqjhllSaGO9Q7x6XJ8IkYPAyYAOByAkEjNZ0NC8MG h+nLT/XqGYWStamS5Y45F/jpfg1hoKxL9yepUQ/POqcT0GSepllGR0aR2EnI+1w5u2MV ToBw== X-Gm-Message-State: AKGB3mJoEKY8QUMPn6mRfiwkWz5MCKzwkRRzURGDgthMeaKHSHuqt5b4 5wrQIVKO9wX+q/2YZLhgn+JTsQ== X-Received: by 10.223.157.206 with SMTP id q14mr11001614wre.21.1515418195160; Mon, 08 Jan 2018 05:29:55 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:54 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 18/20] clocksource/drivers/stm32: Add the clocksource Date: Mon, 8 Jan 2018 14:28:57 +0100 Message-Id: <1515418139-23276-18-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The scene is set for the clocksource, let's add it for this driver. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 1891924..4634f4d 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -80,6 +81,13 @@ static int stm32_timer_of_bits_get(struct timer_of *to) return pd->bits; } +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -204,6 +212,31 @@ static void __init stm32_timer_set_prescaler(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); } +static int __init stm32_clocksource_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); + const char *name = to->np->full_name; + + /* + * This driver allows to register several timers and relies on + * the generic time framework to select the right one. + * However, nothing allows to do the same for the + * sched_clock. We are not interested in a sched_clock for the + * 16bits timers but only for the 32bits, so if no 32bits + * timer registered yet, we select this 32bits timer as a + * sched_clock. + */ + if (bits == 32 && !stm32_timer_cnt) { + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + pr_info("%s: STM32 sched_clock registered\n", name); + } + + return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, + timer_of_rate(to), bits == 32 ? 250 : 100, + bits, clocksource_mmio_readl_up); +} + static void __init stm32_clockevent_init(struct timer_of *to) { u32 bits = stm32_timer_of_bits_get(to); @@ -256,6 +289,10 @@ static int __init stm32_timer_init(struct device_node *node) stm32_timer_set_prescaler(to); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0;