From patchwork Mon Jan 8 13:28:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123712 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727004qgn; Mon, 8 Jan 2018 05:29:54 -0800 (PST) X-Google-Smtp-Source: ACJfBotBjWTXmPzIabHCrMxoq7oDz930SkyJwEGxnOna0dlC2zjDBCCuVjnQ9A9kd3oURTRYKfG0 X-Received: by 10.159.207.129 with SMTP id z1mr11907010plo.18.1515418194314; Mon, 08 Jan 2018 05:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418194; cv=none; d=google.com; s=arc-20160816; b=Yf34D013lJTJzQslEoZDwAAPb3icF1udGRT4LtsVD8B7GjXJcAdHDaTgh9j7M31i5A gZwl3nzsE78FUIVacSCZXw5o23tfGMEpnHCQg36gY4n5CsRq5TGrnceAr/lC2RfU2/CX 0T9/MjGR9U6bZ/Ukrq5s9K+55u+uXsSpw/Fq2IQJYOy/zGZW4wP4du+1mYQPu7nBrsyR tfoLIrFA+7U+Rfvnc6zh2DSPInicRVA6o0gHMX+q8rYBTTitLv+950VMKPzlF2BkmatW HRNfAp//ZDGNcNkNH27NE2/8/XjM+8BEy9exNFaAhtPmT5QNapgpPAjLnGPuQ3GI2Yoy faYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nDOEEh5UOozwDUN/iFWwB3KodhOX8zynnknLsAj1HYg=; b=ZWKNzK3OGVz7OfHkDHVwJ1/OjHY1h623zI2v/gpbdMNns+5VDuKA+UoIzZYQcnyyq3 CPM2kxEPBQR/uOfljqDeW3ZJ8Yx/Q8r3rBpeh3z0n5bDLXi+IFoOVIkkJ7Nnl4lrfLH5 DJ2hB2SG/qkO5v98AJ5B9EZJYbXhYPywh4JSWkS5X4z1JqXH0HCwjQ6udcpMWzAGheuO 65gGfJo3IM3HgOQ5oS0T4v5iYQWpJ4dwmoKlEkxv671+RHS3LLi4w2RyVyjo8ymHoOVJ kMJ8Vo0us81pDJRXgfe0sbSbq1lnctJHWUhGblw+TIQpd5WeYEBXPMxkdQ77+/NM13ix kTQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7LosHk5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r16si7475366pgt.106.2018.01.08.05.29.54; Mon, 08 Jan 2018 05:29:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7LosHk5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933406AbeAHN3v (ORCPT + 28 others); Mon, 8 Jan 2018 08:29:51 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:41819 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933389AbeAHN3s (ORCPT ); Mon, 8 Jan 2018 08:29:48 -0500 Received: by mail-wm0-f65.google.com with SMTP id g75so14220137wme.0 for ; Mon, 08 Jan 2018 05:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nDOEEh5UOozwDUN/iFWwB3KodhOX8zynnknLsAj1HYg=; b=L7LosHk5Myw7nnbnKT5dKmw5KzoSU2+icbIyzw5++bjtcIrVgG/hz33fhkEh6GMPof j5a/k36r8gkMF5VHvUzot4J15Zr1SFuTMuUby2jrPFZpwchrWfR9lRAT7LBQFqIb/mHB tFFnRHFeiECyIGrPJJAiP8gNiXyyAVxYSwk20= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nDOEEh5UOozwDUN/iFWwB3KodhOX8zynnknLsAj1HYg=; b=b4lVJxEZQAaZwsWslQ+dmpRm443+m+Txsom9inNhvVQXs2bbF9PvEZVlb9zQ+mnPLg jB6m9eu6qyScw854JV+X5VYASYDjrcYXl5J1FC0fUETGvoLg9E0NDkpriLo9DvSBzeJE KCy87WW2YeBsucUFvvF07vaou/dpHcS2jVeFhEQQwN74HMUZ2Y5KmyDLU0Qefk4HGvFo 8HTHnb8lgs+PmkZGng3rgziEyOw4Cha6SD+4wxl4j7O/5kR4u9TFONPeEejiOwiXHHNQ 1UMBcgArg146wZXTILrk7G5OA2Rf0SDkvJgA2iHMYi8gekf337MHcORotvGoshHZg1p6 Jv2g== X-Gm-Message-State: AKGB3mIt8WBbiShUoEUIqsVoHkjuNL6dXbFG/aZraKoipMGdNwJxreCT ucUfyq19P2jCAwTt1DpjkIGhOA== X-Received: by 10.28.155.71 with SMTP id d68mr8851943wme.75.1515418187643; Mon, 08 Jan 2018 05:29:47 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:47 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 14/20] clocksource/drivers/stm32: Encapsulate the timer width sorting out function Date: Mon, 8 Jan 2018 14:28:53 +0100 Message-Id: <1515418139-23276-14-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to clarify and encapsulate the code for the next changes move the timer width check into a function and add some documentation. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 14b7a2b..862134e 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -80,9 +80,27 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * stm32_timer_width - Sort out the timer width (32/16) + * @to: a pointer to a timer-of structure + * + * Write the 32bits max value and read/return the result. If the timer + * is a 32bits width, the result will be UINT_MAX, otherwise it will + * be truncated by the 16bits register to USHRT_MAX. + * + * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a + * 16bits width. + */ +static u32 __init stm32_timer_width(struct timer_of *to) +{ + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); + + return readl_relaxed(timer_of_base(to) + TIM_ARR); +} + static void __init stm32_clockevent_init(struct timer_of *to) { - unsigned long max_delta; + u32 width = 0; int prescaler; to->clkevt.name = to->np->full_name; @@ -93,10 +111,8 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { + width = stm32_timer_width(to); + if (width == UINT_MAX) { prescaler = 1; to->clkevt.rating = 250; } else { @@ -115,10 +131,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + timer_of_rate(to), 0x1, width); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, max_delta == UINT_MAX ? 32 : 16); + to->np, width == UINT_MAX ? 32 : 16); } static int __init stm32_timer_init(struct device_node *node)