From patchwork Sat Jan 6 01:10:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 123596 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp40779qgn; Fri, 5 Jan 2018 17:18:40 -0800 (PST) X-Google-Smtp-Source: ACJfBosVIhq0dYC4b8z/dsVcAq8OwJL4QXPYY5joiSy6krqhLH9ogq9L7701lkCL4gBv8OgPquLC X-Received: by 10.84.246.195 with SMTP id j3mr5012580plt.350.1515201520124; Fri, 05 Jan 2018 17:18:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515201520; cv=none; d=google.com; s=arc-20160816; b=F+1ShBOjEae1Bo91bLQI6Cm/xvh93iOEuKRIHPfPK9ogDQoQi+63WNPddxv2wQ0iNj cTo4k72IQb0qMuBKzGMURQWh3GQ468Q+MtiIJsIf89RH1gArl+wNDH6UyxmCO5o4LiKu I8mbiLBaw59KP4lLI9n9cLKgfDnoLhbqhsoW/tnTN435ZkrlGFkM+o3Hsj4zDd3m8VhR BMWQ7FTok3rcBuAlHrrpOCiD03ydOL9k/l3SCrXRULJmKVS9N0nz/3cq1MbMlqIojRDF 6qmStnzFEL4cFjRFH4c93kKpoigPv/9lBfb/EXQ6ZvRS8OV8O0FtuZGr1cP5gwi8GV83 01Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:cc:to:from :subject:arc-authentication-results; bh=g1gi9Cjzcdgn3nDLkHl+niAekyOhnHw8vy3RsjsVl04=; b=rQhKouvbU0dHv1EnhJxyviHILkXZWa1QxBAKxkwf1uM32A/jnJuNKYdheivMffoL0m 1TZx+ySQ0xdMAGmRHu0mnhOVogXxkrs9xNPN59PD1tzCMoX6BMss1rXjldt+VWFLKUVh Ka/f+jdnutYJzbl6LkWwyji74S8x8hW7PihOu9CaLX4FYjrUBimeDYuknCJEz0siLKL4 JYe2pDfN5ZXkn8hFQz6KgAFR2/KV8bIi15CBaUECIu5kNFmt0u1zFhHE8K6Vy8WqAnQJ jEijpHLgSOrvBOJn8W9VCUv3FAX5qwjbOJOVbv2KG8qV0AkMjLTK6+BVkon6y0jOKJlr uLVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e3si4870271pfg.23.2018.01.05.17.18.39; Fri, 05 Jan 2018 17:18:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753702AbeAFBSf (ORCPT + 28 others); Fri, 5 Jan 2018 20:18:35 -0500 Received: from mga04.intel.com ([192.55.52.120]:26995 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753674AbeAFBSc (ORCPT ); Fri, 5 Jan 2018 20:18:32 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jan 2018 17:18:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,320,1511856000"; d="scan'208";a="24777435" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.16]) by orsmga002.jf.intel.com with ESMTP; 05 Jan 2018 17:18:29 -0800 Subject: [PATCH 04/18] arm: implement nospec_ptr() From: Dan Williams To: linux-kernel@vger.kernel.org Cc: Mark Rutland , linux-arch@vger.kernel.org, peterz@infradead.org, netdev@vger.kernel.org, gregkh@linuxfoundation.org, tglx@linutronix.de, torvalds@linux-foundation.org, alan@linux.intel.com Date: Fri, 05 Jan 2018 17:10:14 -0800 Message-ID: <151520101463.32271.9320376934909324865.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <151520099201.32271.4677179499894422956.stgit@dwillia2-desk3.amr.corp.intel.com> References: <151520099201.32271.4677179499894422956.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.17.1-9-g687f MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Rutland This patch implements nospec_ptr() for arm, following the recommended architectural sequences for the arm and thumb instruction sets. Signed-off-by: Mark Rutland Signed-off-by: Dan Williams --- arch/arm/include/asm/barrier.h | 75 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 40f5c410fd8c..6384c90e4b72 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -37,6 +37,81 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifdef CONFIG_THUMB2_KERNEL +#define __load_no_speculate_n(ptr, lo, hi, failval, cmpptr, sz) \ +({ \ + typeof(*ptr) __nln_val; \ + typeof(*ptr) __failval = \ + (typeof(*ptr)(unsigned long)(failval)); \ + \ + asm volatile ( \ + " cmp %[c], %[l]\n" \ + " it hs\n" \ + " cmphs %[h], %[c]\n" \ + " blo 1f\n" \ + " ld" #sz " %[v], %[p]\n" \ + "1: it lo\n" \ + " movlo %[v], %[f]\n" \ + " .inst 0xf3af8014 @ CSDB\n" \ + : [v] "=&r" (__nln_val) \ + : [p] "m" (*(ptr)), [l] "r" (lo), [h] "r" (hi), \ + [f] "r" (__failval), [c] "r" (cmpptr) \ + : "cc"); \ + \ + __nln_val; \ +}) +#else +#define __load_no_speculate_n(ptr, lo, hi, failval, cmpptr, sz) \ +({ \ + typeof(*ptr) __nln_val; \ + typeof(*ptr) __failval = \ + (typeof(*ptr)(unsigned long)(failval)); \ + \ + asm volatile ( \ + " cmp %[c], %[l]\n" \ + " cmphs %[h], %[c]\n" \ + " ldr" #sz "hi %[v], %[p]\n" \ + " movls %[v], %[f]\n" \ + " .inst 0xe320f014 @ CSDB\n" \ + : [v] "=&r" (__nln_val) \ + : [p] "m" (*(ptr)), [l] "r" (lo), [h] "r" (hi), \ + [f] "r" (__failval), [c] "r" (cmpptr) \ + : "cc"); \ + \ + __nln_val; \ +}) +#endif + +#define __load_no_speculate(ptr, lo, hi, failval, cmpptr) \ +({ \ + typeof(*(ptr)) __nl_val; \ + \ + switch (sizeof(__nl_val)) { \ + case 1: \ + __nl_val = __load_no_speculate_n(ptr, lo, hi, failval, \ + cmpptr, b); \ + break; \ + case 2: \ + __nl_val = __load_no_speculate_n(ptr, lo, hi, failval, \ + cmpptr, h); \ + break; \ + case 4: \ + __nl_val = __load_no_speculate_n(ptr, lo, hi, failval, \ + cmpptr, ); \ + break; \ + default: \ + BUILD_BUG(); \ + } \ + \ + __nl_val; \ +}) + +#define nospec_ptr(ptr, lo, hi) \ +({ \ + typeof(ptr) __np_ptr = (ptr); \ + __load_no_speculate(&__np_ptr, lo, hi, 0, __np_ptr); \ +}) + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void);