From patchwork Thu Jan 4 15:08:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123440 Delivered-To: patch@linaro.org Received: by 10.80.135.92 with SMTP id 28csp6823248edv; Thu, 4 Jan 2018 07:12:19 -0800 (PST) X-Google-Smtp-Source: ACJfBotDiYpBQsxbODrX8KKFEDMVvQvqpo4ftKmsyBtGWzp/0Np7raEnZtx0b3KseZXnZSYFVNf0 X-Received: by 10.101.81.76 with SMTP id g12mr82041pgq.150.1515078739677; Thu, 04 Jan 2018 07:12:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515078739; cv=none; d=google.com; s=arc-20160816; b=ZrhRatelMsUb/v3Z7A1YgkyiGPhY7OYfvNL+XMC+QkGntnP71LuxFTNIzZXof01fE1 uv0J61B0Y804O8cwrRoV8CWFmRYJABAqOXFdQXtLRFlXKWcEP49LJc+wXpQb4MZ9Xbn2 MtE5l4bVpPUp7E24DN/MVTBBd2jG4Wiy88EjmkzzGTA/M3/rUsGKYzMQjAedoxtUvY46 E3dgmyLOF43+kYKyjJ2eiolcqMO/K1IIyg5ia8AVjqazlQV8z4Q4WPoUyEzLP+K/fMmg QCzuVELfELRvTzBwc2PRo7A1pZkwzEMESk7cX/7zGAc5zaWtgM3teRDRj1kqVgx71ta5 EQhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jpUYmNEx7VU+s0l/ndx3SHVIXhCGbNw/RkyqJRiZOVc=; b=TWTLTFY5uWO9WbvrVFu3KoHO2FZ/yemVhJNI+CId+PLLgY5vTa9YVlRpE3slFuFDGl TFBCAEjvMuJQ3avKdjMcw010PcEtjD8g4gJp6zH8DrEkmE8Zd1JYAAv3Fb7tDH5OzsxV L33fEXN5dfyH+mflw3ZnpU9jLaus9I0K7bdcLiTGTzsfHQfdWBDTjdJkSCryaXyw0phB f+H8THQ9DJGFPGQHzpTtFQPSkIp4+AtYaju12TXNSoc+NuQR1H2zUvgB3nnxFNR8JFLT eoYeXHpkqHBQ510c1E5VYbBTrXDFgwMyuNWgRY+lxcH7a4G/hS4dJckmoC33tT0Xz9Jr +KLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g62si2148912pgc.428.2018.01.04.07.12.19; Thu, 04 Jan 2018 07:12:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753475AbeADPK3 (ORCPT + 22 others); Thu, 4 Jan 2018 10:10:29 -0500 Received: from foss.arm.com ([217.140.101.70]:33830 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753379AbeADPIm (ORCPT ); Thu, 4 Jan 2018 10:08:42 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8AEDB169F; Thu, 4 Jan 2018 07:08:41 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5C7943F7C7; Thu, 4 Jan 2018 07:08:41 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 0D28C1AE125D; Thu, 4 Jan 2018 15:08:41 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, Will Deacon Subject: [PATCH 10/11] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Thu, 4 Jan 2018 15:08:34 +0000 Message-Id: <1515078515-13723-11-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515078515-13723-1-git-send-email-will.deacon@arm.com> References: <1515078515-13723-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.1.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d98261..84385b94e70b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -79,8 +79,10 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 @@ -94,7 +96,9 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)