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[209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.43; Thu, 04 Jan 2018 04:51:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NNGDscNc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753032AbeADMvk (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:40 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34036 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752990AbeADMvh (ORCPT ); Thu, 4 Jan 2018 07:51:37 -0500 Received: by mail-wr0-f195.google.com with SMTP id 36so1396960wrh.1 for ; Thu, 04 Jan 2018 04:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eL5bvzHTZ4AFS3ok+8f+9iOVrDMHQXywi0pp/m5364g=; b=NNGDscNcwWqvHAZbTEl8EGsDxzFr4MOC1GZJNFrF7WCpoiAA8R0Jk7+Y+f5vLL1Sce f98gJqtkUJR714GmzoSkWrqUw1J3nmXgnKXB6yEHvJqmbaMsZJiCtNqTKIX4kbIFi1m5 8rsaXlbMXlIxLjOPpBpz+6sB7mlxBalNtXOA0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eL5bvzHTZ4AFS3ok+8f+9iOVrDMHQXywi0pp/m5364g=; b=ahR9DASw7JjziEBABp7zmZLhuAfZI9Bh7DZ6EAbLqj//rYezvjYHOumGWEZDONnR1K JVZTSsaPhE/+BS+LudnJzovI2pqB/CQv2sNQG9coPR0rfH2/hghUvjYop8PM10Ri+EfL GWsAvor2iU3BE+KzLjkjjEvnhBfGNsx/3y9wgvwLXbhJV/O/tJoah0UFrq6mSg+Yl9dW LBoWHnZ751zEk+OnfGVtiAoQ/o2cZCCGyEOt+j+hzxfw/38C9JAVa4w3+TIhZYbgFjlo XWnACTbCQZsMWcUBm4Gcyg1SOl6gWQhSk8YkU82DxvSmieLzIz5RZB76ulsSNg+QZYeA iksg== X-Gm-Message-State: AKGB3mIlRoSggcOWuGzpPJg0D8vv70bsuyqvbf3n0u706HwW0Avenmy4 BnwG09jzWkFDV/89KS7vG6cdOw== X-Received: by 10.223.134.115 with SMTP id 48mr4561493wrw.213.1515070296438; Thu, 04 Jan 2018 04:51:36 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:35 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 12/12] clocksource/drivers/stm32: Start the timer's counter sooner Date: Thu, 4 Jan 2018 13:50:28 +0100 Message-Id: <1515070228-10481-13-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As we have a lot of timers on this platform, we can have potentially all the timers enabled in the DT, so we don't want to start the timer for every probe otherwise they will be running for nothing as only one will be used. Start the timer only when setting the mode or when the clocksource is enabled. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index dcf8445..4ce2345 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -101,7 +101,15 @@ static void stm32_clock_event_disable(struct timer_of *to) writel_relaxed(0, timer_of_base(to) + TIM_DIER); } -static void stm32_clock_event_enable(struct timer_of *to) +/** + * stm32_timer_start - Start the counter without event + * @to: a timer_of structure pointer + * + * Start the timer in order to have the counter reset and start + * incrementing but disable interrupt event when there is a counter + * overflow. By default, the counter direction is used as upcounter. + */ +static void stm32_timer_start(struct timer_of *to) { writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); } @@ -137,7 +145,7 @@ static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); } @@ -146,7 +154,7 @@ static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return 0; } @@ -235,6 +243,13 @@ static int __init stm32_clocksource_init(struct timer_of *to) * sched_clock. */ if (bits == 32 && !stm32_timer_cnt) { + + /* + * Start immediately the counter as we will be using + * it right after. + */ + stm32_timer_start(to); + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name);