From patchwork Thu Jan 4 12:50:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123414 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389837qgn; Thu, 4 Jan 2018 04:51:40 -0800 (PST) X-Google-Smtp-Source: ACJfBot/SJU0NFQndqxiaphSuA5ux3EVfWJvyTj55tX106CrGh3Y2HG5mNWYGJcRCGhnHfLB8CM0 X-Received: by 10.84.128.67 with SMTP id 61mr4422982pla.265.1515070300447; Thu, 04 Jan 2018 04:51:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070300; cv=none; d=google.com; s=arc-20160816; b=WXqwxj7/sUMCRkgWM97ldajsm2clIqGfUfk5A4k2hxHuxnjugYWeahZ6jcGegrTNoC G92t/FrXqktZL+G+mcm7M9SSDIOFfca2OleAaFvvxyfNehkrWRRVtRFkMLYVZaj3Ngo3 Zi+MzZTQAD9cxYFuVEh24aJb+p0PB8O8X+Xt5Pc3MSdnfkxz6mcNiD9V2jTUC5kVn8bh +bQQ7e9U+u9oFkwaQ7SsYkkdCVdw/g/cZSbkNYS1S1luhx+pQrgNPbqo4WtG8gBp/mkn lYUQal4pC2Yp9e34AY/dbc3RTC1s5BHME2yZcVbMUlnk8rMasTt+9u+YHV/GP63cd9qk UPZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=m2yDyigNDAmtp+cR1ZbB507rIbAENcswABrZPPwEXx4atNMZlmb52tLiQATs/e3nF4 TcRLLp0K5q+zlBA9sgRfzxuZrx6j/yN3RfFEW4W9fV9av25zI6naZK47Q4hgw7vBoZLd 5c8TUd4CpjfUxtddl+fCtzqIA2C/IRmfUgIn4NxkgQNnTxeA7Wubd3nNr3o8Mi0yUj+g rWTCitIi1Hm83rr5YBtzup9phrUYVZGz7rkfT3RQ9fyk6W4i5hc70SO0NpxcZTirrNIy jMf4a7djPqfyViscV+SFVMSgutbN+p/EuKkggz9dcy7i8z5R37fOyujQF5xdBFrTlYhB dHbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RvQnB+zl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.40; Thu, 04 Jan 2018 04:51:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RvQnB+zl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752992AbeADMvh (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:37 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:36394 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752941AbeADMvd (ORCPT ); Thu, 4 Jan 2018 07:51:33 -0500 Received: by mail-wr0-f195.google.com with SMTP id b76so1402200wrd.3 for ; Thu, 04 Jan 2018 04:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=RvQnB+zlOz7nAyXzX3xkzao5ods8v3Jm/thCc1XPGiZZ5F2VofC25aOMhrupwoewW0 WHG0Cq7qQtEZKDutPrELrWQBnzG824f4h6n9LJjMGO4I4n/jiu2daV9vDByWd28g33GH 5sbwqgzV3WvsbiM3IYGqvCWJ3fajZSEMqN3p4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=bHQewwCKSsI/8SdkThZ6tXP1yF4716HjtWFY+lXSdKChj+MfwvCgfRow+326bw1PA+ B4gDlofWZcFGU320wC/+c+y1v8uwpuV0vBNdYPVwOkk+JcnTRNGNfqF3Od4an44W/4d7 xX/T9HaBY8pXDsjmdjPvc/qHVzKS2mqk6SvTAbEyQdTRpIHBJ9O93cHyXJp8kpbe1mt1 hhrLMTM0HKltd4Sa9rz0eH1HMvkurvHdC5+j9TIBEnthVUxuOahBfFMEIUV17ZBogFRE 2c7FGLOw0E1axCSlnNIEu6qM9OeeXNzlLjBtd9DWKZf3bRAXoM9PdN4xYtV6ftczPBvb S+Cg== X-Gm-Message-State: AKGB3mLK6BlN8ihTlws3pEUZNVZaIjgXxcrroXJRAG67SjwV6bQUHiEn wDNv8olIVpiWlfjBOe8PVQP/mq5RlNI= X-Received: by 10.223.134.134 with SMTP id 6mr4410711wrx.17.1515070292447; Thu, 04 Jan 2018 04:51:32 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:31 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 10/12] clocksource/drivers/stm32: Add the clocksource Date: Thu, 4 Jan 2018 13:50:26 +0100 Message-Id: <1515070228-10481-11-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The scene is set for the clocksource, let's add it for this driver. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 1891924..4634f4d 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -80,6 +81,13 @@ static int stm32_timer_of_bits_get(struct timer_of *to) return pd->bits; } +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -204,6 +212,31 @@ static void __init stm32_timer_set_prescaler(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); } +static int __init stm32_clocksource_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); + const char *name = to->np->full_name; + + /* + * This driver allows to register several timers and relies on + * the generic time framework to select the right one. + * However, nothing allows to do the same for the + * sched_clock. We are not interested in a sched_clock for the + * 16bits timers but only for the 32bits, so if no 32bits + * timer registered yet, we select this 32bits timer as a + * sched_clock. + */ + if (bits == 32 && !stm32_timer_cnt) { + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + pr_info("%s: STM32 sched_clock registered\n", name); + } + + return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, + timer_of_rate(to), bits == 32 ? 250 : 100, + bits, clocksource_mmio_readl_up); +} + static void __init stm32_clockevent_init(struct timer_of *to) { u32 bits = stm32_timer_of_bits_get(to); @@ -256,6 +289,10 @@ static int __init stm32_timer_init(struct device_node *node) stm32_timer_set_prescaler(to); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0;