From patchwork Wed Dec 6 12:35:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120824 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6999605qgn; Wed, 6 Dec 2017 04:36:22 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ52joY6gFumGvb3HpMOyyEw+kOE4PRlVT1VYKGMjpvPnPitIXTedmm3gSmT5DmmAWhHPMQ X-Received: by 10.159.205.139 with SMTP id v11mr176402plo.233.1512563782348; Wed, 06 Dec 2017 04:36:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512563782; cv=none; d=google.com; s=arc-20160816; b=WlOhQIXBEOSUiYTR6I9bXd4cLbajoKn/b2d/dFNv+yQfF5tot//kMHJ/G8mPBbVVCZ w/NzkDG9wcz35iqgjPJCPU6lsGbe5e87vdRWSVDtBHx6jL+qjgUMgcALOLdgJRl8dbId tluWL4TrYVrkx6h5rIa3Ilu4xHWd/99IVDTlWOyXBlZ+UyIyfkx6nih/cWLRGxH24N7C hjfzTbx4J8Q59qD7ZBtj+884sjusdStl9QqmeHiOM7Bz/t+TvUAeriLqKEFmjZ9bfQ+w HS/lR/WLJBhTXjkIfu4wTfUgP9k6cLQuADNyciZzyxSKxXW6S5yZdjqAmbA/Nzl0+UY4 X9jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=zI2qYtDRi6Q9X+xGgw4GyZcMFvHTlFZq4mxjaPEOJLk=; b=s7NMS2OyaEy7y3vzqZieCre3/7Ns+BQ/PGR02b2ZGu5rcG+n4PwyVICstcM0/pKNvr u8eXBwEPhH2VW1v2nLUDiSzZC3iFaCCnojCA5xyUMfUfj4fXEF8ZafHXJCu3rv9G1x4+ Z3dP7iaJdfUyBYynaxM77dC7i5lxj0IMuzfYamtLmLjJ4ImwlgKiMZuIA88p36QsHzIu rdcq+tcf2TT+oWVaJPTQjqbkzKAZnXW3lT8gI1ydEXJ0TrrYsuKb4Vtar7K2sTMFhWtD Lp+ROmUNPOGI4Fq79vyaAS0BBQIRCvNp/MolL98qYg73rEvpe/woldWe4ggdUYeKPQer oQ8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f8si1924185pli.451.2017.12.06.04.36.22; Wed, 06 Dec 2017 04:36:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752312AbdLFMgU (ORCPT + 28 others); Wed, 6 Dec 2017 07:36:20 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751847AbdLFMgK (ORCPT ); Wed, 6 Dec 2017 07:36:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 842F91610; Wed, 6 Dec 2017 04:36:10 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5589E3F627; Wed, 6 Dec 2017 04:36:10 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id EB9B91AE3603; Wed, 6 Dec 2017 12:36:15 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v3 03/20] arm64: mm: Move ASID from TTBR0 to TTBR1 Date: Wed, 6 Dec 2017 12:35:22 +0000 Message-Id: <1512563739-25239-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512563739-25239-1-git-send-email-will.deacon@arm.com> References: <1512563739-25239-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Reviewed-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/include/asm/mmu_context.h | 7 +++++++ arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/include/asm/proc-fns.h | 6 ------ arch/arm64/mm/proc.S | 9 ++++++--- 4 files changed, 14 insertions(+), 9 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 3257895a9b5e..2d63611e4311 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -57,6 +57,13 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } +static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) +{ + BUG_ON(pgd == swapper_pg_dir); + cpu_set_reserved_ttbr0(); + cpu_do_switch_mm(virt_to_phys(pgd),mm); +} + /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index eb0c2bd90de9..8df4cb6ac6f7 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h index 14ad6e4e87d1..16cef2e8449e 100644 --- a/arch/arm64/include/asm/proc-fns.h +++ b/arch/arm64/include/asm/proc-fns.h @@ -35,12 +35,6 @@ extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include -#define cpu_switch_mm(pgd,mm) \ -do { \ - BUG_ON(pgd == swapper_pg_dir); \ - cpu_do_switch_mm(virt_to_phys(pgd),mm); \ -} while (0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 95233dfc4c39..a8a64898a2aa 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,9 +139,12 @@ ENDPROC(cpu_do_resume) */ ENTRY(cpu_do_switch_mm) pre_ttbr0_update_workaround x0, x2, x3 + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 + bfi x2, x1, #48, #16 // set the ASID + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + isb + msr ttbr0_el1, x0 // now update TTBR0 isb post_ttbr0_update_workaround ret @@ -224,7 +227,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /*