From patchwork Wed Dec 6 12:35:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120831 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7001801qgn; Wed, 6 Dec 2017 04:38:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMbnzuDc3YURcw8SVfyP4JW8d7yjItFUVBT2+fGVSmqwz0TNEG0/+KGHtbEFTOY6q0X7TGOf X-Received: by 10.99.109.73 with SMTP id i70mr5810859pgc.134.1512563916539; Wed, 06 Dec 2017 04:38:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512563916; cv=none; d=google.com; s=arc-20160816; b=Wlhdick5L4ydQ44dwXPa34Yhc9DCvYNB9XpchjnmR1j5INJnSphTsdaX1A31Xxg8Je TQFU84LRQYPJ/JDQejW/tFrE1iwPgg42Yc2XCQVVQx1rXDtCScxs3q9ZodQB0nsg+Iq9 c0PWmgp5g393zvx1fZl2f3n26RSRh0uNNnKyRAwvRp9EmFz3eXoA5N30yiCm7guoh2le sonYM4OFR38S7Z145XN3o/Iq1HxlGeUb0X9inXjMt265inAL97JDUcf+jKkJ3czUAxP+ 3zEXpiegWDwpbFzTEhgRyaogO+V0TuAieQtl+V4gz3rHdCyjA/ZJBTkjM2bPmTjy/aYF 6sNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=d6TeP91CE/95IFaqza+mFJrdaUY+71l0IehiCKcx9w8=; b=aVy/XqAAUItGXqPY0e7RrJBshSiJdzE4USTyAziRSOZGtUhm5ZxsRakvGoSSO+M3uj C88dz586v6JNMJgsBUZgTtluTRiUBM7EiWkgq3wcQ3NzXrn/jBcgX+wgEgqYs/VH4+qZ vq2DfNfK9PEQoFYCZkdfz9kiw06R3Y13lHc6LLylzn8LZOCEvHb/GZBzce6/Tt8xVew7 Q3/L9B4v/iCEx5qnoqiBYtMyWLOm2yvkVdUAn7/oXDAe8pvNKk2s6rMFduk8d8jxkXyd o121gZjyNN+/tNOdkN3bh2eKRqIN9WSuixiW4LoMzFTPlm/cj2gejH4BGciO0KG/0m7C Up/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s59si1910014plb.232.2017.12.06.04.38.36; Wed, 06 Dec 2017 04:38:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752298AbdLFMif (ORCPT + 28 others); Wed, 6 Dec 2017 07:38:35 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34686 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752177AbdLFMgM (ORCPT ); Wed, 6 Dec 2017 07:36:12 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C34781713; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 952BB3F627; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id DF1D31AE3564; Wed, 6 Dec 2017 12:36:16 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v3 15/20] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks Date: Wed, 6 Dec 2017 12:35:34 +0000 Message-Id: <1512563739-25239-16-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512563739-25239-1-git-send-email-will.deacon@arm.com> References: <1512563739-25239-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When unmapping the kernel at EL0, we use tpidrro_el0 as a scratch register during exception entry from native tasks and subsequently zero it in the kernel_ventry macro. We can therefore avoid zeroing tpidrro_el0 in the context-switch path for native tasks using the entry trampoline. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/kernel/process.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index b2adcce7bc18..aba3a1fb492d 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -361,16 +361,14 @@ void tls_preserve_current_state(void) static void tls_thread_switch(struct task_struct *next) { - unsigned long tpidr, tpidrro; - tls_preserve_current_state(); - tpidr = *task_user_tls(next); - tpidrro = is_compat_thread(task_thread_info(next)) ? - next->thread.tp_value : 0; + if (is_compat_thread(task_thread_info(next))) + write_sysreg(next->thread.tp_value, tpidrro_el0); + else if (!arm64_kernel_unmapped_at_el0()) + write_sysreg(0, tpidrro_el0); - write_sysreg(tpidr, tpidr_el0); - write_sysreg(tpidrro, tpidrro_el0); + write_sysreg(*task_user_tls(next), tpidr_el0); } /* Restore the UAO state depending on next's addr_limit */