From patchwork Wed Dec 6 12:35:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120835 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7002003qgn; Wed, 6 Dec 2017 04:38:49 -0800 (PST) X-Google-Smtp-Source: AGs4zMbOwasM90X6QPJ0sFDC9DjE3bYRNZSN/B8n0uEpju1XZaYEX3NUgLReAtwd+O8HmXp+gVXj X-Received: by 10.84.131.68 with SMTP id 62mr6673764pld.185.1512563929370; Wed, 06 Dec 2017 04:38:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512563929; cv=none; d=google.com; s=arc-20160816; b=whQBZu2J9zp95Zcp/EXBhp7vLDlZe0772uI9vUCNu9KPbU4QHOQGIJjH7qaH7QUTPV 9bzlZsDWJYIH1+KPGmT+qBTUmkFAxHGR0/47tsossI+TatX4lMXDjGP+GSGW96UEiPt5 hVDgrIZwI2++WO8ugPRzRxA7GQcoGgD8W37trMUXmUrva5ABhjHcicQWMHY5iSJDvp3p 9EouT1Lj/WfoxMsr6Nvq9ia2lWFd67D5fZI0BRV4zvVErLm01CD1/QwWsQna3kWX+qJ6 8Xm4SH+CZlru2gwgS8cYfoRnAtvqJMlq1xUFl2SS4UbBDnENUwTqFTt3AdhKPc69TuOf Z3Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=c4AjNLTQvdi08vPHUO6iM1ed2QLNFvT2kvw7HDZFCfc=; b=wKTsC44kb0LYcEdefx0jRq8fjR9EFzEfhp4GmB2e8ge0KpcZhgd2r9bYvh6EC/UCg/ PKO0i0OIPWg11Pbd6QjJNzJdwQk4jGVpTaOZRltXxeddSXOwn3WimJYEzgpXnWHMruqY Q6/1pE9Z7T30dlZVvhnW/IC4ImrKjDjEvJFLcvNqMa31RwBb+5gbCCUGPvwXRXEbCgPg GKJT+RjfelpNDdPLzsb4kR3e/0kmPD5c6QMBnrfmJlrFUuR1xz40LrZp2/LOvunrGE+Q pq1N7HXUjkvNPwo1B25bXeMEMyvx5cN5vaduf3ycMFOhVOSxDpCcMfQALlH/NxR5Q0cP GgmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 89si1949624plf.200.2017.12.06.04.38.48; Wed, 06 Dec 2017 04:38:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752642AbdLFMir (ORCPT + 28 others); Wed, 6 Dec 2017 07:38:47 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34782 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752162AbdLFMgM (ORCPT ); Wed, 6 Dec 2017 07:36:12 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F11C16BA; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 70C8E3F7C5; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id B3D5B1AE38AD; Wed, 6 Dec 2017 12:36:16 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v3 13/20] arm64: entry: Hook up entry trampoline to exception vectors Date: Wed, 6 Dec 2017 12:35:32 +0000 Message-Id: <1512563739-25239-14-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512563739-25239-1-git-send-email-will.deacon@arm.com> References: <1512563739-25239-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up the entry trampoline to our exception vectors so that all exceptions from and returns to EL0 go via the trampoline, which swizzles the vector base register accordingly. Transitioning to and from the kernel clobbers x30, so we use tpidrro_el0 and far_el1 as scratch registers for native tasks. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/kernel/entry.S | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index b99fc928119c..39e3873b8d5a 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -73,6 +73,17 @@ .macro kernel_ventry, el, label, regsize = 64 .align 7 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + .if \el == 0 + .if \regsize == 64 + mrs x30, tpidrro_el0 + msr tpidrro_el0, xzr + .else + mov x30, xzr + .endif + .endif +#endif + sub sp, sp, #S_FRAME_SIZE #ifdef CONFIG_VMAP_STACK /* @@ -119,6 +130,11 @@ b el\()\el\()_\label .endm + .macro tramp_alias, dst, sym + mov_q \dst, TRAMP_VALIAS + add \dst, \dst, #(\sym - .entry.tramp.text) + .endm + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 @@ -271,18 +287,20 @@ alternative_else_nop_endif .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer msr sp_el0, x23 + tst x22, #PSR_MODE32_BIT // native task? + b.eq 3f + #ifdef CONFIG_ARM64_ERRATUM_845719 alternative_if ARM64_WORKAROUND_845719 - tbz x22, #4, 1f #ifdef CONFIG_PID_IN_CONTEXTIDR mrs x29, contextidr_el1 msr contextidr_el1, x29 #else msr contextidr_el1, xzr #endif -1: alternative_else_nop_endif #endif +3: .endif msr elr_el1, x21 // set up the return data @@ -304,7 +322,22 @@ alternative_else_nop_endif ldp x28, x29, [sp, #16 * 14] ldr lr, [sp, #S_LR] add sp, sp, #S_FRAME_SIZE // restore sp - eret // return to kernel + +#ifndef CONFIG_UNMAP_KERNEL_AT_EL0 + eret +#else + .if \el == 0 + bne 4f + msr far_el1, x30 + tramp_alias x30, tramp_exit_native + br x30 +4: + tramp_alias x30, tramp_exit_compat + br x30 + .else + eret + .endif +#endif .endm .macro irq_stack_entry