From patchwork Tue Dec 5 16:13:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 120693 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5889537qgn; Tue, 5 Dec 2017 07:32:00 -0800 (PST) X-Google-Smtp-Source: AGs4zMaGLm9NgBKb4/zLr3I1pdmxOWAWD3sYaNZt+B6C2BQjWcStHjTpzqDPD3nSpsQ1Vh6lh0fx X-Received: by 10.84.174.129 with SMTP id r1mr18967635plb.337.1512487920316; Tue, 05 Dec 2017 07:32:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512487920; cv=none; d=google.com; s=arc-20160816; b=a1e92X0gWpVcQDncPnpnS0jCIZbCk02i7j/syXoi1y6gXva9uY3PuX/f9U7liGLIdh P76Ku3f6iIpQg8VWKq7qfAyxPgYx/FVuNREsEGWR/pgrauT7FcXnu0c3d/1jTWrGGOTi RR45apHMelioQ985JnGOMWLaXy3Z2a02RBeOOqm0AjDV3eeguCgK4HKvmWJPBaMFV9Kp hds59/Zx35fL3HE418+jsMv3SpUm8i7rgz4F3htHAlOmBYuiG291V7iNmhEp8RLRvTRc JI/ABrUjFa3Rif4D+h15UmNbllqWTkuSZXhVwc0Sdj0iW3iYdiuQwAsJm2BvcqKWP3bW uSiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=aXKE2l2e4zeQtRXj/gi/sdM1BtwgBBRvHld7W+4TSls=; b=RCZ/acIsCIdP1W46MZasLgOFLbCl+EmLMmidy/O3fX1WHNn4DgXCGpg277GVbjf3+y LXnl53NzI4fBlZPT2xqRDNbf+VEaFXm+P/veKPtb2F+oUPHDDX9LvGIpXAU+9BZeyqhV edtwPswNuyIE0KP66lsfXTugWJTM4htizow3uq0s4WciAKEAsQPirBI6HMvoMqRiqrjQ A+0oK0HjaMVm0tPrb9JIEOIo21r+9W4z3yp/BpaYD4LOAKAjA0bgdn4kwj5qIQ1Ca3KC FCT794PlM8x/ul48q3C0+6K7z6qIjUG8cq64P+339pN4l3L3xqc2Z+34gShZdjXMM5jn oijg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6si234193pfs.283.2017.12.05.07.31.59; Tue, 05 Dec 2017 07:32:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753039AbdLEPb6 (ORCPT + 28 others); Tue, 5 Dec 2017 10:31:58 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2210 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752592AbdLEPb3 (ORCPT ); Tue, 5 Dec 2017 10:31:29 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9FAC58F833B8D; Tue, 5 Dec 2017 23:31:13 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 5 Dec 2017 23:31:04 +0800 From: John Garry To: , , , , , , , , , , , CC: , , , , , John Garry Subject: [RFC PATCH 5/5] perf vendor events arm64: add HiSilicon hip08 JSON Date: Wed, 6 Dec 2017 00:13:19 +0800 Message-ID: <1512490399-94107-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512490399-94107-1-git-send-email-john.garry@huawei.com> References: <1512490399-94107-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add HiSilicon hip08 JSON. Since hip08 has its events implementated according to ARM recommendation, only add fields "EventCode" (where applicable - hip08 also has implemented some other custom events). Signed-off-by: John Garry Signed-off-by: Shaokun Zhang --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 123 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 0000000..94fde40 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,122 @@ +[ + { + "EventCode": "0x40", + }, + { + "EventCode": "0x41", + }, + { + "EventCode": "0x42", + }, + { + "EventCode": "0x43", + }, + { + "EventCode": "0x46", + }, + { + "EventCode": "0x47", + }, + { + "EventCode": "0x48", + }, + { + "EventCode": "0x4C", + }, + { + "EventCode": "0x4D", + }, + { + "EventCode": "0x4E", + }, + { + "EventCode": "0x4F", + }, + { + "EventCode": "0x50", + }, + { + "EventCode": "0x51", + }, + { + "EventCode": "0x52", + }, + { + "EventCode": "0x53", + }, + { + "EventCode": "0x56", + }, + { + "EventCode": "0x57", + }, + { + "EventCode": "0x58", + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 32fa0d1..9cc42da 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -13,3 +13,4 @@ # #Family-model,Version,Filename,EventType 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core