From patchwork Tue Dec 5 16:13:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 120691 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5889299qgn; Tue, 5 Dec 2017 07:31:49 -0800 (PST) X-Google-Smtp-Source: AGs4zMa9XGzjNYRSe8j4VytYwcbUzFuAVY14gshDSUNYZwAmiSyajenb7Pgmvn3EkHuo+OO6oP1g X-Received: by 10.98.65.197 with SMTP id g66mr23545439pfd.60.1512487909335; Tue, 05 Dec 2017 07:31:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512487909; cv=none; d=google.com; s=arc-20160816; b=c3UUySPN292JKrdU08pOurzhLHqZ6JnSXM+rTfU2yymq6R0PM99UFgdXFbCI0+Q90m 7X7F99YDOSi6T3QixEGHpKyLI0KMYWOYv1p1dqrvEKmk4+n0rndOL6F2pQrzkdlUU2LU uReLwbNsi5/o113H3PPP1PRhtob9eIKTPrr9l+qxlBNPs/5UsO3kQqzVfDJajiL9Zvza eFSUwbCYOjChEpWTzACn/foiA+AnRNXCp54nxv2otW1Sken3uDm9rYLgvI1kAMVfySe8 L8ZEgPqJV5nmYUyFXgB4DQ4b2ofbyZ8xcbg+RbZK9XIqfNX0T0jTNOZdbPiX9OtlgGox /33A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Ql12s1oOCLOJ9rugFjjehLeEa4JzKWoVG1XyXKjswwE=; b=pTwWZair1F1Qq1Zg+cOGBm/shqUy5hnEX1nd0ZJWin8Aaa1xKo+lhuPBJMIHhf6QjG WE/Ra2eiBqcLbYJuSnOiIm8sVpXnkRiyxnDSV/bbuUIBxRmO0ncC0VOFgXXMvhPvgTN5 GbiT4gGrtLLqT87j/euJRhhbdDZmPwLW0O2sVCejD2j5bC1GHq5E/ep/vN5Q4PZQlWY1 AoYknHE+U4QCJ0YhV7Y8BleBj59UhFvk1Z6GsepDXdUlEXJ9Rv9dMn6JhgwsmfqfqxEY Ky2vpW41RelkfOfFu4UnRZWqnUPIlvH2Bv4J41ERT33n/I+CdsjsaCVj4/yS6EuCM7du yjRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6si234193pfs.283.2017.12.05.07.31.49; Tue, 05 Dec 2017 07:31:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752844AbdLEPb2 (ORCPT + 28 others); Tue, 5 Dec 2017 10:31:28 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2255 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752592AbdLEPbY (ORCPT ); Tue, 5 Dec 2017 10:31:24 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 33717EF25C6D2; Tue, 5 Dec 2017 23:31:08 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 5 Dec 2017 23:31:04 +0800 From: John Garry To: , , , , , , , , , , , CC: , , , , , John Garry Subject: [RFC PATCH 4/5] perf vendor events arm64: relocate thunderx2 JSON Date: Wed, 6 Dec 2017 00:13:18 +0800 Message-ID: <1512490399-94107-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512490399-94107-1-git-send-email-john.garry@huawei.com> References: <1512490399-94107-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since the pmu events architecture folder structure supports arch/vendor/platform structure, relocate the ThunderX2 JSON. Also since Cavium ThunderX2 has implemented its events according to ARM recommendation, remove the fields apart from "EventCode". Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---------------------- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 32 +++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 3 files changed, 33 insertions(+), 63 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json deleted file mode 100644 index 2db45c4..0000000 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json +++ /dev/null @@ -1,62 +0,0 @@ -[ - { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", - }, - { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", - }, - { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", - }, - { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json new file mode 100644 index 0000000..99313eb --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -0,0 +1,32 @@ +[ + { + "EventCode": "0x40", + }, + { + "EventCode": "0x41", + }, + { + "EventCode": "0x42", + }, + { + "EventCode": "0x43", + }, + { + "EventCode": "0x4C", + }, + { + "EventCode": "0x4D", + }, + { + "EventCode": "0x4E", + }, + { + "EventCode": "0x4F", + }, + { + "EventCode": "0x60", + }, + { + "EventCode": "0x61", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 219d675..32fa0d1 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,4 +12,4 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core