From patchwork Thu Nov 30 16:39:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120236 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp20946qgn; Thu, 30 Nov 2017 08:46:46 -0800 (PST) X-Google-Smtp-Source: AGs4zMYmOUQzV3GeZcGkVTwgf+QwGCEcI0nK2agEw+7CeEKiR7kgPXoPsD1v//MwDaPSuKIUp+4T X-Received: by 10.159.205.131 with SMTP id v3mr3297712plo.139.1512060406801; Thu, 30 Nov 2017 08:46:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512060406; cv=none; d=google.com; s=arc-20160816; b=SuXgmEF7JjwnPNhKBfbIZvn77xHVOKNI3LkmJmEzZRH7GbeHrTg/KAij8U0hz+NZPm myaYdb5kWWdyz83w3cDo8LuxQBWm2iNUzhfJ0ofMXVs7DphO1UZdh0AsyD0SiQR7kLFd zpx+V0+i6F9HERKHEuDY9wsKnGxKCH+f7RcAiQJoxJ7TiBnimwxJoOr5taA7q+6hv/5I 8VcNh6QjnjmjR4OdJ7K3w4XUswblSLtKNzPCs1S2atj2J9W2LnOZfUGPFSTVEG0sM74w 1EGxKvjB6aAJPS8oARHPrhEbUVlocATCtxFBOPU1XvWDUW46g/AC7GE9/kuPTXemMbNY o9Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VysFSLKlA8MSUliu3avseHdHs0kUjW7mQ1mSd0bpIlo=; b=HNXIc5+YmiYXQdZGB/DHNR3wwHlVs0xpRHnwm6+zJU9/KQpj2bj7SacyJUdADEb6PG PNKm9rrH+QtdzFAiMdY09Z0TS2cXz0HrPyDN6PyOEXHJ0MnJRBr2XQ5tb7+08o1QQIyw Z6TV7ImM200F/xb/cScBpAmUmaW04tv6lLQ+x7f+vIKY/oBo+H1Huy287u2tS0puLE3K graNNQS7/4MsRxnVIeowN2FIuqHa61Edt/aJBeaCt9jp98WJLTRSk3pOQo5lCMsZz5Jb uyivpjYFHaPOt2gn9Y1zrZ2Nv0ovdFra/JQvOX03Gw5ILJr5db9DhX8rAJUju0ZcroTi i4Nw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a62si3268320pli.333.2017.11.30.08.46.46; Thu, 30 Nov 2017 08:46:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753383AbdK3QqP (ORCPT + 28 others); Thu, 30 Nov 2017 11:46:15 -0500 Received: from foss.arm.com ([217.140.101.70]:57482 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753313AbdK3Qjp (ORCPT ); Thu, 30 Nov 2017 11:39:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5293F164F; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2416F3F318; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id C521C1AE3D59; Thu, 30 Nov 2017 16:39:47 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v2 05/18] arm64: mm: Rename post_ttbr0_update_workaround Date: Thu, 30 Nov 2017 16:39:33 +0000 Message-Id: <1512059986-21325-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512059986-21325-1-git-send-email-will.deacon@arm.com> References: <1512059986-21325-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1. Since we're using TTBR1 for the ASID, rename the hook to make it clearer as to what it's doing. Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 5 ++--- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/proc.S | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index e1fa5db858b7..c45bc94f15d0 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -477,10 +477,9 @@ alternative_endif .endm /* -/* - * Errata workaround post TTBR0_EL1 update. + * Errata workaround post TTBRx_EL1 update. */ - .macro post_ttbr0_update_workaround + .macro post_ttbr_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 6d14b8f29b5f..804e43c9cb0b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -257,7 +257,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr0_update_workaround + post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f2ff0837577c..3146dc96f05b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr0_update_workaround + post_ttbr_update_workaround ret ENDPROC(cpu_do_switch_mm)