From patchwork Thu Nov 30 16:39:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120233 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp18234qgn; Thu, 30 Nov 2017 08:44:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMaTGqYHlk4uJYh/mw51d4QixWH8kNAvqSvebN9MhuIyY/3COkCms0Ei3RqKABTFKw8F81KW X-Received: by 10.98.34.199 with SMTP id p68mr7109008pfj.241.1512060258619; Thu, 30 Nov 2017 08:44:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512060258; cv=none; d=google.com; s=arc-20160816; b=x6xEiIp43RP+M7ezYZXZ2kpUUTx1AbXCcQKwUic572Nrvw8PoGpXnZ4u7DxGITSUfH oJHP6SLuyuxu2LcTa8G/TE+4Zjc7WOj+UkiAcOtYiIvNM8J/ifzJDCladMFrOpwjUOY+ ZtAS3y06i9+csv13x+HtOc1cqED2zud8eHODQHU0X9WdOgLpiiT3DOZODyj2izYANdfE 12td0pcOkxqz0/1Y9OdS1hmA47cjGxntknSLPlUc7/5xez+sl1p1yHzL8ueSdIoxVM6y EYjL0NAQvc//tD7PA0n4QYe8AY/2d1EjF1ca71YpO68TZi7QxsFz1suAFG9IasgAH4Qw 8CkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=7n3TAd51rVdguA3E+x++XQjmkPp4kPr/lYjjB5J/AFo=; b=HYxmo3087cXv9rGBoCPd6gSobSuEFCk7sY1AZraDRaNTUpSj4ePEeLj9JvDPv7MDKK 2bJbKFqxnTiZm/EH9S99s4TjOm9LBcJMxKch6asAV1LzCsdfkJHaLdzJH5C+QIrZklpT aETMo/ZSIqf4OycyH5XRpg6XB/70cqOOPfHby/8Rvg6/9qDOPrCiHoBH+LuHndbyv0nT vYrbLR3WjXjGYAdF0y8EWFZGTYQRwD1nSJLrAKhcIK8nlAt7CLI3mwBSY1ly2ipIh37k eoUkhhxUk5yMiTcuFKtlFiruekEdtGjligabP5l81EFKl5P/7FMKar4tmWoIjWsT00Hc 8khg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g68si3231268pgc.304.2017.11.30.08.44.18; Thu, 30 Nov 2017 08:44:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753543AbdK3QnV (ORCPT + 28 others); Thu, 30 Nov 2017 11:43:21 -0500 Received: from foss.arm.com ([217.140.101.70]:57560 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753350AbdK3Qjq (ORCPT ); Thu, 30 Nov 2017 11:39:46 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A11219CC; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6BC933F5B7; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 47F501AE3DFB; Thu, 30 Nov 2017 16:39:48 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v2 13/18] arm64: entry: Hook up entry trampoline to exception vectors Date: Thu, 30 Nov 2017 16:39:41 +0000 Message-Id: <1512059986-21325-14-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512059986-21325-1-git-send-email-will.deacon@arm.com> References: <1512059986-21325-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up the entry trampoline to our exception vectors so that all exceptions from and returns to EL0 go via the trampoline, which swizzles the vector base register accordingly. Transitioning to and from the kernel clobbers x30, so we use tpidrro_el0 and far_el1 as scratch registers for native tasks. Signed-off-by: Will Deacon --- arch/arm64/kernel/entry.S | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 688e52f65a8d..99d105048663 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -73,6 +73,17 @@ .macro kernel_ventry, el, label, regsize = 64 .align 7 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + .if \el == 0 + .if \regsize == 64 + mrs x30, tpidrro_el0 + msr tpidrro_el0, xzr + .else + mov x30, xzr + .endif + .endif +#endif + sub sp, sp, #S_FRAME_SIZE #ifdef CONFIG_VMAP_STACK /* @@ -119,6 +130,11 @@ b el\()\el\()_\label .endm + .macro tramp_alias, dst, sym + mov_q \dst, TRAMP_VALIAS + add \dst, \dst, #(\sym - .entry.tramp.text) + .endm + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 @@ -271,18 +287,20 @@ alternative_else_nop_endif .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer msr sp_el0, x23 + tst x22, #PSR_MODE32_BIT // native task? + b.eq 3f + #ifdef CONFIG_ARM64_ERRATUM_845719 alternative_if ARM64_WORKAROUND_845719 - tbz x22, #4, 1f #ifdef CONFIG_PID_IN_CONTEXTIDR mrs x29, contextidr_el1 msr contextidr_el1, x29 #else msr contextidr_el1, xzr #endif -1: alternative_else_nop_endif #endif +3: .endif msr elr_el1, x21 // set up the return data @@ -304,7 +322,22 @@ alternative_else_nop_endif ldp x28, x29, [sp, #16 * 14] ldr lr, [sp, #S_LR] add sp, sp, #S_FRAME_SIZE // restore sp - eret // return to kernel + +#ifndef CONFIG_UNMAP_KERNEL_AT_EL0 + eret +#else + .if \el == 0 + bne 4f + msr far_el1, x30 + tramp_alias x30, tramp_exit_native + br x30 +4: + tramp_alias x30, tramp_exit_compat + br x30 + .else + eret + .endif +#endif .endm .macro irq_stack_entry