From patchwork Fri Nov 17 18:21:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119209 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp846766qgn; Fri, 17 Nov 2017 10:25:53 -0800 (PST) X-Google-Smtp-Source: AGs4zMZb47hZcr4gStX6kIrt04p5q0/vpA6TeRE5Seet3omOPL7XLw+GJXb662WTbJCTZXYm4OPR X-Received: by 10.98.186.13 with SMTP id k13mr2947258pff.166.1510943153044; Fri, 17 Nov 2017 10:25:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943153; cv=none; d=google.com; s=arc-20160816; b=YtuRlhzBSIDhlAh7ldVLDox8R9KUu+rYNR8spq5c34RVc12MH8dK0T5fb3TDehULCo s1sazm/LE6cg4vstqSiI1JXpnQk+Ncix9KTrbFOXYTMqHV8vbDw1Dai0PRAhNTX8P+FI 1GZDlgGISddPdi75Tdq1D+aG6iMAS7Jn7uFYOn0eyjJQCHkKgAhwU0PRiDUa5WpsMzD/ Wki/5V65S8B9/TeWN5qBPx3/uY0dKI8oGf6hgDTuEY5+ozkYcmolmswno/g2f00C7Nti Opil8VS4yp5rucO0ZAgcdGHod4ufhjGqKUvVbZRBAa4Uh4jMNiKM7O5B7+ChztD7gt/U jK8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=nES7YSTX0iBPY/vJFLeLQOZ7UisrY/vSSQKxE2q4SNU=; b=EBk2WzikHlN0wtowy0IPf9UqjFBROZMvW688UX8tHgqQQmAK+ffh/W4dGOH2hASmiD 4bWjescbGLjSP79nEatoxdhy51zpTVi8VT1u1kigNptz7tHs8/3We+b2X53pXUOwg2SI eQJ9khjruP+GsFa6xHHfQCOfSO3AaHMbTMM09h9bNW1mZkWpKdNYQ3m9cSwQk3lN7gWR ONmLJaq/UoHqVLsjwK8XCWL4HsdNHdiJ4kwqr+yaeoctTp8Ml0nC3sFua0M9z/9iaiCQ Lrtxd2YaUIPmsY8xRjSrs+WUA67sOyQ8Qipw4C2hdKCeRrWD3dghfiaKWriy+97CUrpc NXJA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i76si3066875pgc.416.2017.11.17.10.25.52; Fri, 17 Nov 2017 10:25:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760668AbdKQSZu (ORCPT + 28 others); Fri, 17 Nov 2017 13:25:50 -0500 Received: from foss.arm.com ([217.140.101.70]:39416 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760284AbdKQSVz (ORCPT ); Fri, 17 Nov 2017 13:21:55 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7C90165C; Fri, 17 Nov 2017 10:21:54 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B97733F246; Fri, 17 Nov 2017 10:21:54 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 2BF871AE11F5; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 05/18] arm64: mm: Rename post_ttbr0_update_workaround Date: Fri, 17 Nov 2017 18:21:48 +0000 Message-Id: <1510942921-12564-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1. Since we're using TTBR1 for the ASID, rename the hook to make it clearer as to what it's doing. Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 5 ++--- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/proc.S | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8359148858cb..622316a8c82b 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -464,10 +464,9 @@ alternative_endif .endm /* -/* - * Errata workaround post TTBR0_EL1 update. + * Errata workaround post TTBRx_EL1 update. */ - .macro post_ttbr0_update_workaround + .macro post_ttbr_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e1c59d4008a8..dd5fa2c3d489 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -255,7 +255,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr0_update_workaround + post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1623150ed0a6..447537c1699d 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr0_update_workaround + post_ttbr_update_workaround ret ENDPROC(cpu_do_switch_mm)