From patchwork Fri Nov 17 18:21:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119211 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp847065qgn; Fri, 17 Nov 2017 10:26:13 -0800 (PST) X-Google-Smtp-Source: AGs4zMYm708OkWXB83rsrIg/2/fLLr1xrr5nHxkBtrIkZteyK+3fp5vR5vSh83RH7KuTqPU8dg2V X-Received: by 10.101.80.10 with SMTP id f10mr5949821pgo.408.1510943173515; Fri, 17 Nov 2017 10:26:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943173; cv=none; d=google.com; s=arc-20160816; b=W+pVBdm242n03qGRuz8qVFlVM7rXRGyI5tz15/LHh0CfMkwzOOMMpM7r1b7EHGsMc6 Et6GkbJF4kYCjwG0NfHbMbYHlczBCM84Aj0oDFNKui2kykLRPcUg0WqZxIFIadeR+SkW IwKGSaaCKEwJUlcI7bIv5br4Wc75O5AjobYR4PuinOK1/n4TbBsM8wDltdnZsCrjUcrQ W+JERxRMhlP94GL5hRiQ6CMxXNXF3CTKxPSrKYDlKTpVxIu5s8+S1rg5Rklvv3SdWpdf oY6m+ONQe4Se/Cugf5P0AY6sY1T0a+PHCS0cQkNLvNYEYKHavynsHAEA6+LCwK/CRXCf LzyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jTDRWgyYREJkYO6ZVBLae8Gm6Wg8YvPPSr+hkriqxJo=; b=znec30tiyyXrJ7/yzd2UEVGeJ3xtzOXANIOXuZM3JI6vSsd1cPsJqH8yOEKqDfzN9L Xolpu7ENRuavcCyVb3gIhF1sWAo3WFHo3+H11UQ/4ABpRLPM/iaUbnru6eU9uLr0tptB NMdVrdnRnyK4qmgzho4iMU5ZqaEc2f0XYob90DyyJXjZ4jioMZv+xlLZ5/4fOOAsvnOv T97TFwTb0Wz34QLmDECN6GwSvKx5sx3MDt7SSUhQzc3iRVie4eUsSdQ/2iQh8PrhaTeL wJt5NoBJ2UVC6kxZSeBwufa5Sl6LkCTHMJLL/RuhCH3TghUtSjtpK8WLTzaztMUaTMOY hgSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v18si3149802pge.275.2017.11.17.10.26.13; Fri, 17 Nov 2017 10:26:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760676AbdKQS0K (ORCPT + 28 others); Fri, 17 Nov 2017 13:26:10 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39304 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760277AbdKQSVy (ORCPT ); Fri, 17 Nov 2017 13:21:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E8461610; Fri, 17 Nov 2017 10:21:54 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 000103F703; Fri, 17 Nov 2017 10:21:53 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 117A91AE1116; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 03/18] arm64: mm: Move ASID from TTBR0 to TTBR1 Date: Fri, 17 Nov 2017 18:21:46 +0000 Message-Id: <1510942921-12564-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Signed-off-by: Will Deacon --- arch/arm64/include/asm/mmu_context.h | 7 +++++++ arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/include/asm/proc-fns.h | 6 ------ arch/arm64/mm/proc.S | 9 ++++++--- 4 files changed, 14 insertions(+), 9 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 3257895a9b5e..56723bcbfaaa 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -37,6 +37,13 @@ #include #include +#define cpu_switch_mm(pgd,mm) \ +do { \ + BUG_ON(pgd == swapper_pg_dir); \ + cpu_set_reserved_ttbr0(); \ + cpu_do_switch_mm(virt_to_phys(pgd),mm); \ +} while (0) + static inline void contextidr_thread_switch(struct task_struct *next) { if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index eb0c2bd90de9..8df4cb6ac6f7 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h index 14ad6e4e87d1..16cef2e8449e 100644 --- a/arch/arm64/include/asm/proc-fns.h +++ b/arch/arm64/include/asm/proc-fns.h @@ -35,12 +35,6 @@ extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include -#define cpu_switch_mm(pgd,mm) \ -do { \ - BUG_ON(pgd == swapper_pg_dir); \ - cpu_do_switch_mm(virt_to_phys(pgd),mm); \ -} while (0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 877d42fb0df6..0bd7550b7230 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,9 +139,12 @@ ENDPROC(cpu_do_resume) */ ENTRY(cpu_do_switch_mm) pre_ttbr0_update_workaround x0, x2, x3 + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 + bfi x2, x1, #48, #16 // set the ASID + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + isb + msr ttbr0_el1, x0 // now update TTBR0 isb post_ttbr0_update_workaround ret @@ -225,7 +228,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /*